UNIT-V

SEQUENTIAL CIRCUITS

A sequential circuit is a logical circuit, where the output depends on the present value
of the input signal as well as the sequence of past inputs. While a combinational
circuit is a function of present input only. A sequential circuit is a combination of
combinational circuit and a storage element. the sequential circuits use current input
variables and previous input variables which are stored and provides the data to the
circuit on the next clock cycle.

Block diagram

Types of Sequential Circuits

The sequential circuits are classified into two types

 Synchronous Circuit
 Asynchronous Circuit
In synchronous sequential circuits, the state of device changes at discrete times in
response to a clock signal. In asynchronous circuits, the state of the device changes in
response to changing inputs.
Synchronous Circuits

In synchronous circuits, the inputs are pulses with certain restrictions on pulse width
and propagation delay. Thus synchronous circuits can be divided into clocked and un-
clocked or pulsed sequential circuits.

Synchronous Circuit

Asynchronous Circuits

An asynchronous circuit does not have a clock signal to synchronize its internal changes
of the state. Hence the state change occurs in direct response to changes that occur in
primary input lines. An asynchronous circuit does not require the precise timing control
from flip-flops.

Asynchronous Circuit
Asynchronous logic is more difficult to design and it has some problems compared to
synchronous logic. The main problem is that the digital memory is sensitive to the order
that their input signals arrive them, like, if two signals arrive at a flip-flop at the same
time, which state the circuit goes into can depend on which signal gets to the logic gate
first.

Asynchronous circuits are used in critical parts of synchronous systems where the
speed of the system is a priority, like as in microprocessors and digital signal processing
circuits.

Flip Flop

Flip flop is a sequential circuit which generally samples its inputs and changes its
outputs only at particular instants of time and not continuously. Flip flop is said to be
edge sensitive or edge triggered rather than being level triggered like latches.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also
called as level triggered SR-FF. For this, circuit in output will take place if and only if
the enable input (E) is made active. In short this circuit will operate as an S-R latch if E
= 1 but there is no change in the output if E = 0.

Block Diagram

Circuit Diagram
Truth Table

SR Characteristic Table
.

Present Inputs Present State Next State State

S R Qn Qn+1

0 0 0 0 No change

0 0 1 1

0 1 0 0 Reset

0 1 1 0

1 0 0 1 Set

1 0 1 1

1 1 0 x Invalid

1 1 1 x

Operation

S.N. Condition Operation

1 S = R = 0 : No change
If S = R = 0 then output of NAND gates 3 and 4 are forced
to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are
 the input of the basic S-R latch using NAND gates, there
will be no change in the state of outputs.

2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the
output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S'
= 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar =
0. This is the reset condition.

4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and
4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND
latch.

SR flip-flop Excitation Table

("X" is "don't care")

States Inputs

Present Next S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0
Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second
to input of first. Master is a positive level triggered. But due to the presence of the
inverter in the clock line, the slave will respond to the negative level. Hence when the
clock = 1 (positive level) the master is active and the slave is inactive. Whereas when
clock = 0 (low level) the slave is active and master is inactive.

Circuit Diagram

Truth Table

JK Flip Flop Characteristic Table

Present Inputs Present State Next State State

S R Qn Qn+1

0 0 0 0 No change

0 0 1 1

0 1 0 0 Reset
 0 1 1 0

1 0 0 1 Set

1 0 1 1

1 1 0 x Toggle

1 1 1 x

JK flip-flop Excitation Table

("X" is "don't care")

States Inputs

Present Next J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Operation

S.N. Condition Operation

1 J = K = 0 (No change)
When clock = 0, the slave becomes active and master is
inactive. But since the S and R inputs have not changed,
the slave outputs will also remain unchanged. Therefore
outputs will not change if J = K =0.
2 J = 0 and K = 1 (Reset)
Clock = 1 − Master active, slave inactive. Therefore
outputs of the master become Q1 = 0 and Q1 bar = 1. That
means S = 0 and R =1.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 0 and Q bar = 1.
Again clock = 1 − Master active, slave inactive. Therefore
even with the changed outputs Q = 0 and Q bar = 1 fed
back to master, its output will be Q1 = 0 and Q1 bar = 1.
That means S = 0 and R = 1.
Hence with clock = 0 and slave becoming active the
outputs of slave will remain Q = 0 and Q bar = 1. Thus we
get a stable output from the Master slave.

3 J = 1 and K = 0 (Set)
Clock = 1 − Master active, slave inactive. Therefore
outputs of the master become Q1 = 1 and Q1 bar = 0. That
means S = 1 and R =0.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the outputs of
the slave are stabilized to Q = 1 and Q bar = 0.

4 J = K = 1 (Toggle)
Clock = 1 − Master active, slave inactive. Outputs of
master will toggle. So S and R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of slave
will toggle.
These changed output are returned back to the master
inputs. But since clock = 0, the master is still inactive. So it
does not respond to these changed outputs. This avoids
the multiple toggling which leads to the race around
condition. The master slave flip flop will avoid the race
around condition.
Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data is appearing
at the output after some time. Due to this data delay between i/p and o/p, it is called
delay flip flop. S and R will be the complements of each other due to NAND inverter.
Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is
avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram
Truth Table

D Flip Flop Characteristic Table

Inputs Present State Next State

D Qn Qn+1

0 0 0

0 1 0

1 0 1

1 1 1

Operation

S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.

2 E = 1 and D = 0
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the
reset condition.

3 E = 1 and D = 1
If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and
Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.
D flip-flop Excitation Table

States Input

Present Next D

0 0 0

0 1 1

1 0 0

1 1 1

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T as shown in the Symbol Diagram.
The symbol for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram
Block Diagram

Truth Table

T Flip Flop Characteristic Table

Inputs Present State Next State

T Qn Qn+1

0 0 0

0 1 1

1 0 1

1 1 0
Operation

S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock

signal.

T flip-flop Excitation Table:

States Input

Present Next T

0 0 0

0 1 1

1 0 1

1 1 0
Synchronous Counter

Definition: The synchronous counter is a type of counter in which the clock signal is
simultaneously provided to each flip-flop present in the counter circuit. More specifically, we
can say that each flip-flop is triggered in synchronism with the clock input.

Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following flip flop is driven by output of previous flip
flops. We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pu lse
is encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like
clock pulse for second flip flop) and so on. In this way ripples are generated through
Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter.
Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop.

Synchronous counter circuit

Timing diagram synchronous counter

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1
is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
 Designing of Synchronous Mod-N Counters

Example 1: Design a mod – 5 synchronous counters using JK flip-flop.

Solution:

A mod-5 counter counts from 0 to 4. Thus, following the steps given in article - designing of
synchronous counter, a mod-5 counter can be designed as:

Step 1: The number of flip-flops required to design a mod-5 counter can be calculated using the
formula: 2n >= N, where n is equal to no. of flip-flop and N is the mod number. In this case, the
possible value on n which satisfies the above equation is 3. Hence, the required number of flip-
flops is 3.

Step 2: The type of flip-flop required to design the counter is JK flip-flop.

Step 3: We can draw the state diagram for mod-5 counter describing the state flow in current and
next state as:

Step 4: Using the excitation table of JK flip-flop, we need to obtain the flip-flop inputs
for each state that we obtained in the third step and now we will enter it into a table as:
Step 5: Making K-Map for each input combination and simplifying it to get the
minimized Boolean expression.

.
Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required
counter circuit which can be shown as:

Example 2: Design a mod - 10 synchronous counter/ Decade counter/ BCD

counter using T flip-flop

Solution:

A mod-10 counter counts from 0 to 9. Thus, following the steps given in the article - designing
of synchronous counter, a mod-10 counter can be designed as:

Step 1: The number of flip-flops required to design a mod-10 counter can be calculated using the
formula: 2n >= N, where n is equal to no. of flip-flop and N is the mod number. In this case, the
possible value on n which satisfies the above equation is 4. Hence, the required number of flip-
flops is 4.

Step 2: The type of flip-flop required to design the counter is T flip-flop.

Step 3: We can draw the state diagram for mod-10 counter describing the state flow in current
and next state as:
Step 4: Using the excitation table of T flip-flop, we need to obtain the flip-flop inputs for each
state that we obtained in the third step and now we will enter it into a table as:

Step 5: Making K-Map for each input combination and simplifying it to get the minimized
Boolean expression.
Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required counter
circuit which can be shown as:
Synchronous 3 bit Up/Down counter
 These types of counters fall under the category of synchronous controller counter.
 Here the mode control input is used to decide whether which sequence will be
generated by the counter.
 In this case, mode control input is used to decide whether the counter will perform up
counting or down counting.
 Designing of such a counter is the same as designing a synchronous counter but the
extra combinational logic for mode control input is required.
Steps to design Synchronous 3 bit Up/Down Counter :
1. Decide the number and type of FF –
 Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are
required, which can count up to 23-1 = 7.
 Here T Flip Flop is used.
2. Write excitation table of Flip Flop –

Excitation table of T FF

3. Decision for Mode control input M –

 When M=0 ,then the counter will perform up counting.
 When M=1 ,then the counter will perform down counting.
4. Draw the state transition diagram and circuit excitation table –
 State transition diagram for 3 bit up/down counting.

5. Circuit excitation table –

The circuit excitation table represents the present states of the counting sequence and the next
states after the clock pulse is applied and input T of the flip-flops. By seeing the transition
between the present state and the next state, we can find the input values of 3 Flip Flops using
the Flip Flops excitation table. The table is designed according to the required counting
sequence.
Circuit excitation table

If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0), then the
corresponding T value becomes 1 otherwise 0.
6. Find a simplified equation using k map –
Here we are finding the minimal Boolean expression for each Flip Flop input T using k map.

Simplified equation for K map

7. Create a circuit diagram –

The simplified expression for Flip Flops is used to design circuit diagrams. Here all the
connections are made according to simplified expressions for Flip Flops.
 3 bit synchronous up/down counter.

8. Timing Diagram –

Timing diagram for 3 bit synchronous Up/Down counter

 Shift Registers in Digital Logic
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store
multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to
store n bits of data. A Register is a device which is used to store such information. It is a group
of flip flops connected in series used to store multiple bits of data.
The information stored within these registers can be transferred with the help of shift
registers. Shift Register is a group of flip flops used to store multiple bits of data. The bits
stored in such registers can be made to move within the registers and in/out of the registers by
applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where
each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in a serial pattern, th us the name
Serial-In Serial-Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of
four D flip-flops which are connected in a serial manner. All these flip-flops are synchronous
with each other since the same clock signal is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop. The main use of a SISO is to act as a delay element.
Serial-In Parallel-Out shift Register (SIPO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the
clock signal to all the 4 flip flops in order to RESET them. The output of the first flip flop is
connected to the input of the next flip flop and so on. All these flip-flops are synchronous with
each other since the same clock signal is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop and producing a parallel output. They are used in communication lines
where demultiplexing of a data line into several parallel lines is required because the main use
of the SIPO register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift
register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists
of four D flip-flops which are connected. The clock input is directly connected to all the flip
flops but the input data is connected individually to each flip flop through a multiplexer at the
input of every flip flop. The output of the previous flip flop and parallel data input are
connected to the input of the MUX and the output of MUX is connected to the next flip flop.
All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip flop.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out
shift register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal and clock signals are
connected to all the 4 flip flops. In this type of register, there are no interconnections between
the individual flip-flops since no serial shifting of the data is required. Data is given as input
separately for each flip flop and in the same way, output also collected individually from each
flip flop.
A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.

Bidirectional Shift Register –

If we shift a binary number to the left by one position, it is equivalent to multiplying the
number by 2 and if we shift a binary number to the right by one position, it is equivalent to
dividing the number by 2.To perform these operations we need a register which can shift the
data in either direction.
Bidirectional shift registers are the registers which are capable of shifting the data either right
or left depending on the mode selected. If the mode selected is 1(high), the data will be shifted
towards the right direction and if the mode selected is 0(low), the data will be shifted towards
the left direction.
The logic circuit given below shows a Bidirectional shift register. The circuit consists of four
D flip-flops which are connected. The input data is connected at two ends of the circuit and
depending on the mode selected only one and gate is in the active state.
Shift Register Counter

Shift Register Counters are the shift registers in which the outputs are connected back to the
inputs in order to produce particular sequences. These are basically of two types:
Ring Counter –
A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed
back to the input of the first flip flop, thus the name ring counter. The data pattern within
the shift register will circulate as long as clock pulses are applied.
The logic circuit given below shows a Ring Counter. The circuit consists of four D flip-
flops which are connected. Since the circuit consists of four flip flops the data pattern will
repeat after every four clock pulses as shown in the truth table below:

A Ring counter is generally used because it is self-decoding. No extra decoding circuit is

needed to determine what state the counter is in.
Johnson Counter –
A Johnson counter is basically a shift register counter in which the output of the first flip
flop is connected to the next flip flop and so on and the inverted output of the last flip flop
is again fed back to the input of the first flip flop. They are also known as twisted ring
counters.
The logic circuit given below shows a Johnson Counter. The circuit consists of four D flip -
flops which are connected. An n-stage Johnson counter yields a count sequence of 2n
different states, thus also known as a mod-2n counter. Since the circuit consists of four flip
flops the data pattern will repeat every eight clock pulses as shown in the truth table below:

The main advantage of Johnson counter is that it only needs n number of flip-flops
compared to the ring counter to circulate a given data to generate a sequence of 2n states.
Applications of shift Registers –

 The shift registers are used for temporary data storage.

 The shift registers are also used for data transfer and data manipulation.
 The serial-in serial-out and parallel-in parallel-out shift registers are used to produce
time delay to digital circuits.
 The serial-in parallel-out shift register is used to convert serial data into parallel data
thus they are used in communication lines where demultiplexing of a data line into
several parallel line is required.
 A Parallel in Serial out shift register us used to convert parallel data to serial data.

Read Only Memory (ROM) – Working, Types, Applications, Advantages &

Disadvantages
ROM is the acronym for Read Only Memory. ROM is a type of Primary Memory. As the name
suggests its contents can be read only but cannot write on it. It is a non-volatile memory and so
the data is retained even when the power is switched off.

The data that is required to be stored inside ROM is written during manufacturing phase. It stores
such programs that are essential for the booting process of the computer. It generally cannot be
altered. However, technologies are available to program these types of ROM.
 Fig.1 – Classification of Primary Memory

How Read Only Memory (ROM) Works

A ROM operates like an array. ROM chips contain a grid of rows and columns to turn ON or
OFF. It uses a diode to connect the lines if the value is 1. If the value is 0, then these lines are not
connected at all. Each element of the array corresponds to one storage element in the memory
chip.

The address input to the chip is employed to pick out a specific memory location (corresponding
to the array index). The value read from the memory chip corresponds to the contents of the
selected element of the array.
 Fig.2 – Diode Grid in Read Only Memory (ROM)

ROM consists of two basic components- Decoder and OR gates. In ROM, the input to decoder
will be in binary form and output will be its decimal equivalent. All the OR Gates present in the
ROM will take decoders output as their input.

Types of Read Only Memory (ROM)

ROM is differentiated on the basis of methods used to write data on ROM chips and the number
of times they can be written. It can be classified into following types : –

 Mask Read-Only Memory (MROM)

 Programmable Read-Only Memory (PROM)
 Erasable Programmable Read-Only Memory (EPROM)
 Electrically Erasable Programmable Read-Only Memory (EEPROM)
 Flash Read-Only Memory (Flash ROM)
Mask Read Only Memory (MROM)

MROM stands for Mask Read Only Memory. It is a memory chip that is manufactured with its
contents. These are inexpensive and are the very first ROMs which were hard wired devices that
contain a pre-programmed set of data or instructions.

Fig. 3 – Mask Read Only Memory (MROM)

These chips contain a software mask that is burned onto the chip during design phase of the
semiconductor manufacturing process.

The specification of the ROM is taken by the manufacturer from its customer in tabular form and
in a particular format. The manufacturer then makes the corresponding mask for the paths to
produce the desired output.

Applications of Mask Read Only Memory (MROM)

The Mask Read-Only Memory (MROM) are used for:

 Network Operating Systems.

 Server Operating Systems.
 Storing fonts for laser printers.
 Storing sound data in electronic musical instruments.

Advantage of Mask Read Only Memory (MROM)

The main advantage of Mask Read-Only Memory (MROM) is its low production cost. The cost
of IC depends on its size, per bit. Mask ROM is more compact. It is significantly cheaper than
any other kind of secondary memory when large quantities of same ROM are manufactured.

Disadvantage of Mask Read Only Memory (MROM)

Design errors are costly i.e. if an error in the code is detected, the MROM is useless and must be
replaced in order to change the code. The life expectancy of MROM is also short, hence requires
frequent replacement.

Programmable Read Only Memory (PROM)

PROM stands for Programmable Read Only Memory. PROM is manufactured as a blank
memory. And as its name suggests Programmable, it is programmed after manufacturing. The
user buys a blank memory and enters the desired contents using a PROM program.
 Fig. 4 – Programmable Read Only Memory (PROM)

The process of programming a PROM is called burning the PROM. There are tiny fuses in a
PROM chip which are burnt open during programming. The data can be programmed only once
and cannot be altered. So it is called one- time programming device.

Applications of Programmable Read Only Memory (PROM)

The Programmable ROM (PROM) are used in:

 Mobile Phones for providing User Specific Selections.

 Video game consoles
 Implantable Medical devices.
 Radio-Frequency Identification (RFID)tags.
 High definition Multimedia Interfaces(HDMI)

Advantages of Programmable Read Only Memory (PROM)

The advantages of Programmable ROM (PROM) are: –

 The programming can be done using many types of software and does not rely on hard
wiring of the program to the chip.
 Since it is not possible to un-blow the fuse, so the authenticity of the data remains intact
and it is impossible to remove or alter the contents.

Disadvantage of Programmable Read Only Memory (PROM)

The biggest disadvantage of PROM is that the data once burnt cannot be erased or changed when
detected with errors.

Erasable Programmable Read Only Memory (EPROM)

EPROM stands for Erasable Programmable Read-Only Memory. It is a non volatile memory i.e.
it can retain data even if the power supply is cut off. The basic limitation being encountered in
PROM is that once it is programmed, it cannot be changed or altered. This limitation has been
overcame by EPROM.

EPROM can be erased by exposing it to ultra violet light for a particular length of time using an
EPROM eraser. After exposing, the chip returns to its initial state and can be reprogrammed.
This procedure can be carried out many times but repeated erasing and rewriting can eventually
render the chip useless. Once written, data can be retained for about 10 years.

Fig. 5 – Erasable Programmable Read Only Memory (EPROM)

Applications of Erasable Programmable Read Only Memory (EPROM)

The applications of Erasable Programmable ROM (EPROM) include:

 As program storage chip in Micro controllers.

 For debugging.
 For program development.
 As BIOS chip in computers.
 As program storage chip in modem, video card and many electronic gadgets.

Advantages of Erasable Programmable Read Only Memory (EPROM)

The advantages of Erasable Programmable ROM (EPROM) are:

 It is non-volatile.
 It can be erased and re -programmed.
 It is cost effective as compared to PROM.

Disadvantages of Erasable Programmable Read Only Memory (EPROM)

The disadvantages of Erasable Programmable ROM (EPROM) are:

 The static power consumption is high as the transistors used have higher resistance.
 It is not possible for a particular byte to be erased, instead the entire content is erased.
 UV based EPROM takes time to erase the content.

Electrically Erasable Programmable Read Only Memory (EEPROM)

EEPROM is the short form for Electrically Erasable Programmable Read Only Memory. It is
similar to EPROM and thus developed to overcome the drawbacks of EPROMs. It is erased and
programmed electrically i.e. it uses electrical signals instead of ultra violet rays.

The erasing and programming of data takes 4 to 10 milliseconds. Any byte can be erased at a
time instead of the entire chip. The chip can be erased and re programmed for around ten
thousand times, though the process is flexible but slow.

Applications of Electrically Erasable Programmable Read Only Memory (EEPROM)

The applications of Electrically Erasable Programmable ROM (EPROM) includes:

 As BIOS chip in computers

 As storage for re-programmable calibration information in test-equipment.
 As storage for in-built self learning functionality in remote operated transmitters.

Advantages of Electrically Erasable Programmable Read Only Memory (EEPROM)

The advantages of Electrically Erasable Programmable ROM (EEPROM) are:

 The method of erasing is electrical and instant.

 Chip can be reprogrammed infinite number of times.
 Byte wise data can be erased instead of entire content on the board.
 To change the data, additional devices are not required.
Disadvantages of Electrically Erasable Programmable Read Only Memory (EEPROM)

The disadvantages of Electrically Erasable Programmable ROM (EEPROM) are:

 Different voltages are required for erasing, reading and writing the data.
 The data retention period of EEPROM is limited i.e 10 years approx.
 EEPROM devices are expensive compared to others.

Flash Read Only Memory (Flash ROM)

It is a universal flash programming non volatile utility, used in computer as a storage medium. It
can be electrically erased and reprogrammed. In this, memory blocks of data (512 bytes) can be
deleted and written at a particular time.

Fig. 7 – Flash Read Only Memory (Flash-ROM)

Applications of Flash Read Only Memory (Flash ROM)

The applications of Flash Read-Only Memory (Flash ROM) are:

 The latest technology computers use BIOS stored on a flash memory chip, called as flash
BIOS.
 Modems, pen drives, small cards use flash ROM.
Advantages of Flash Read Only Memory (Flash ROM)

The Advantages of Flash Read-Only Memory (Flash ROM) are:

 High transferring speed.

 It saves data when turns OFF, preserve its state without power.
 Less prone to damage.
 Comparatively economical to other drives in small storage capacities.

Disadvantages of Flash Read Only Memory (Flash ROM)

The disadvantages of Flash Read-Only Memory (Flash ROM) are:

 Comparatively costly than hard disk.

 Number of read/writes are limited.

Random Access Memory

RAM (Random Access Memory) is the internal memory of the CPU for storing data, program,
and program result. It is a read/write memory which stores data until the machine is working.
As soon as the machine is switched off, data is erased.
Access time in RAM is independent of the address, that is, each storage location inside the
memory is as easy to reach as other locations and takes the same amount of time. Data in the
RAM can be accessed randomly but it is very expensive.
RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a
power failure. Hence, a backup Uninterruptible Power System (UPS) is often used with
computers. RAM is small, both in terms of its physical size and in the amount of data it can
hold.
RAM is of two types −

 Static RAM (SRAM)

 Dynamic RAM (DRAM)

Static RAM (SRAM)

The word static indicates that the memory retains its contents as long as power is being
supplied. However, data is lost when the power gets down due to volatile nature. SRAM chips
use a matrix of 6-transistors and no capacitors. Transistors do not require power to prevent
leakage, so SRAM need not be refreshed on a regular basis.
There is extra space in the matrix, hence SRAM uses more chips than DRAM for the same
amount of storage space, making the manufacturing costs higher. SRAM is thus used as cache
memory and has very fast access.

Static RAM (SRAM) is a type of random access memory that retains its state for data bits or
holds data as long as it receives the power. It is made up of memory cells and is called a static
RAM as it does not need to be refreshed on a regular basis because it does not need the power to
prevent leakage, unlike dynamic RAM. So, it is faster than DRAM.

It has a special arrangement of transistors that makes a flip-flop, a type of memory cell. One
memory cell stores one bit of data. Most of the modern SRAM memory cells are made of six
CMOS transistors, but lack capacitors. The access time in SRAM chips can be as low as 10
nanoseconds. Whereas, the access time in DRAM usually remains above 50 nanoseconds.

Furthermore, its cycle time is much shorter than that of DRAM as it does not pause between
accesses. Due to these advantages associated with the use of SRAM, It is primarily used for
system cache memory, and high-speed registers, and small memory banks such as a frame buffer
on graphics cards.

The Static RAM is fast because the six-transistor configuration of its circuit maintains the flow
of current in one direction or the other (0 or 1). The 0 or 1 state can be written and read instantly
without waiting for the capacitor to fill up or drain. The early asynchronous static RAM chips
performed read and write operations sequentially, but the modern synchronous static RAM chips
overlap read and write operations.

Characteristic of Static RAM

 Long life
 No need to refresh
 Faster
  Used as cache memory
 Large size
 Expensive
 High power consumption

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order to maintain the data. This is
done by placing the memory on a refresh circuit that rewrites the data several hundred times per
second. DRAM is used for most system memory as it is cheap and small. All DRAMs are made
up of memory cells, which are composed of one capacitor and one transistor.

Dynamic Ram (DRAM) is also made up of memory cells. It is an integrated circuit (IC) made of
millions of transistors and capacitors which are extremely small in size and each transistor is
lined up with a capacitor to create a very compact memory cell so that millions of them can fit on
a single memory chip. So, a memory cell of a DRAM has one transistor and one capacitor and
each cell represents or stores a single bit of data in its capacitor within an integrated circuit.

The capacitor holds this bit of information or data, either as 0 or as 1. The transistor, which is
also present in the cell, acts as a switch that allows the electric circuit on the memory chip to read
the capacitor and change its state.

The capacitor needs to be refreshed after regular intervals to maintain the charge in the capacitor.
This is the reason it is called dynamic RAM as it needs to be refreshed continuously to maintain
its data or it would forget what it is holding. This is achieved by placing the memory on a refresh
circuit that rewrites the data several hundred times per second. The access time in DRAM is
around 60 nanoseconds.
Characteristics of Dynamic RAM

 Short data lifetime

 Needs to be refreshed continuously
 Slower as compared to SRAM
 Used as RAM
 Smaller in size
 Less expensive
 Less power consumption
Difference between Static RAM and Dynamic RAM:
SRAM
It is a static memory as it does not need
to be refreshed repeatedly.
Its memory cell is made of 6 transistors.
So its cells occupy more space on a chip
and offer less storage capacity
(memory) than a DRAM of the same
physical size.
It is more expensive than DRAM and is
located on processors or between a
processor and main memory.
It has a lower access time, e.g. 10
nanoseconds. So, it is faster than
DRAM.
It stores information in a bistable
latching circuitry. It requires regular
power supply so it consumes more
power.
It is faster than DRAM as its memory
cells don't need to be refreshed and are
always available. So, it is mostly used in
registers in the CPU and cache memory
of various devices.
Its cycle time is shorter as it does not
need to be paused between accesses and
refreshes.
Examples: L2 and LE cache in a CPU.
Size ranges from 1 MB to 16MB.
DRAM
It is a dynamic memory as it needs to be
refreshed continuously or it will lose the
data.
Its memory cell is made of one transistor
and one capacitor. So, its cells occupy less
space on a chip and provide more memory
than a SRM of the same physical size.
It is less expensive than SRAM and is
mostly located on the motherboard.
It has a higher access time, e.g. more than
50 nanoseconds. So, it is slower than
SRAM.
The information or each bit of data is
stored in a separate capacitor within an
integrated circuit so it consumes less
power.
It is not as fast as SRAM, as its memory
cells are refreshed continuously. But still,
it is used in the motherboard because it is
cheaper to manufacture and requires less
space.
Its cycle time is more than the SRAM's
cycle time.
Example: DDR3, DDR4 in mobile phones,
computers, etc.
Size ranges from 1 GB to 3 GB in
smartphones and 4GB to 16GB in laptops.
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Applications of Multiplexer

Multiplexer are used in various fields where multiple data need to be transmitted using
a single line. Following are some of the applications of multiplexers –

1. Communication System – Communication system is a set of system that enables

communication like transmission system, relay and tributary station, and
communication network. The efficiency of communication system can be
increased considerably using multiplexer. Multiplexer allow the process of
transmitting different type of data such as audio, video at the same time using a
single transmission line.
2. Telephone Network – In telephone network, multiple audio signals are
integrated on a single line for transmission with the help of multiplexers. In this
way, multiple audio signals can be isolated and eventually, the desire audio
signals reach the intended recipients.
3. Computer Memory – Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of copper lines
required to connect the memory to other parts of the computer circuit.
4. Transmission from the Computer System of a Satellite – Multiplexer can be
used for the transmission of data signals from the computer system of a satellite
or spacecraft to the ground system using the GPS (Global Positioning System)
satellites.
 Master-Slave JK Flip Flop
What is a Master-Slave Flip Flop?
Basically, this type of flip flop can be designed with two JK FFs by connecting in series. One of
these FFs, one FF works as the master as well as other FF works as a slave. The connection of
these FFs can be done like this, the master FF output can be connected to the inputs of the slave
FF. Here slave FF’s outputs can be connected to the inputs of the master FF.

In this type of FF, an inverter is also used addition to two FFs. The inverter connection can be
done in such a way that where the inverted CLK pulse can be connected to the slave FF. In other
terms, if CLK pulse is 0 for a master FF, then CLK pulse will be 1 for a slave FF. Similarly,
when CLK pulse is 1 for master FF, then CLK pulse will be 0 for slave FF.

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long
period of time, then Q output will toggle as long as CLK is high, which makes the output of the
flip-flop unstable or uncertain. This problem is called race around condition in J-K flip-flop. This
problem (Race Around Condition) can be avoided by ensuring that the clock input is at logic “1”
only for a very short time. This introduced the concept of Master Slave JK flip flop.

Master Slave JK flip flop –The Master-Slave Flip-Flop is basically a combination of two JK
flip-flops connected together in a series configuration. Out of these, one acts as the “master” and
the other as a “slave”. The output from the master flip flop is connected to the two inputs of the
slave flip flop whose output is fed back to inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected
to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other
words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip
flop then it becomes 0 for slave flip flop.
Working of a master slave flip flop –
When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the
system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.
Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the
clock forces the slave to reset, thus the slave copies the master.
If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles
on the negative transition of the clock.
If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

1.When the Clock pulse is high the output of master is high and remains high till the clock is low
because the state is stored.
2.Now the output of master becomes low when the clock pulse becomes high again and remains
low until the clock becomes high again.
3.Thus toggling takes place for a clock cycle.
4.When the clock pulse is high, the master is operational but not the slave thus the output of the
slave remains low till the clock remains high.
5.When the clock is low, the slave becomes operational and remains high until the clock again
becomes low.
6.Toggling takes place during the whole process since the output is changing once in a cycle.
This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with
the timing of the clock signal.