Fourth Y. B.Tech.

(Electronics & Telecommunication)

Question Bank on CMOS VLSI Design

Q. 1. Solve any four: [4 X 4 =16 Marks]

a. When Vgs of MOSFET with threshold voltage of 0.4 V, working in saturation region is
0.9 V, the drain current is observed to be 1 mA. Find the drain current if Vgs is 1.4 V.
b. Draw stick diagram of NAND gate.
c. Draw stick diagram of NOR gate.
d. Draw stick diagram of inverter.
e. Design NOR gate using CMOS logic.
f. Draw NAND gate using CMOS logic.
g. Design NOR gate using ratioed logic.
h. Design NAND gate using ratioed logic.
i. Differentiate between static and dynamic design in CMOS.
j. If supply voltage is 3 V and load capacitance is 5 fF, then calculate the amount of energy
stored on the capacitor.
k. If supply voltage is 3 V and load capacitance is 5 fF, then calculate the amount of energy
stored on the capacitor.
l. Define scaling. Explain the various types of scaling.
m. Design buffer using CMOS logic.
n. Explain the concept of dynamic CMOS logic with the help of example.
o. List out the various second order effects in MOS transistor.

Q.2. Solve any two: [2 X 6 = 12 Marks]

a. Explain various modes of operation in MOS transistor.
b. Explain the concept of Power, Energy and Energy Delay Product. If the load
capacitance is 6 fF and supply voltage is 2.5 V, then calculate the energy required
to charge and discharge the capacitance.
c. Obtain the current equations for MOS transistor in the cut off, non-saturation and
saturation region.
 d. Explain the various signal integrity issues in Dynamic CMOS logic design.
e. Design 4:1 multiplexer using CMOS logic.
f. Explain the static and dynamic power dissipation for CMOS inverter. Obtain the
expression for total power dissipation.
g. Explain the following with respect to CMOS inverter:
i. Switching threshold ii. Noise Margin
h. Define threshold voltage for MOS transistor. Also, explain with the help of
equations various factors on which it depends.
i. Explain the various second order effects in MOS transistor.

Q. 3. Solve any four: [4 X 4 = 16 marks]

a. Explain multiplexer based positive latch.
b. Explain the concept of bistability principle.
c. Explain the concept of dynamic transmission-gate edge triggered registers.
d. Define the timing properties of registers.
e. Explain low voltage static latches.
f. Explain static SR flip flop.
g. Explain synchronizer with the help of neat diagram.
h. Explain clock skew and clock jitter.
i. Explain Wallace tree for 4 – bit multiplier.
j. Explain how PLL can be used to synchronize the clock.
k. Explain the concept of CLA adder with the help of equations.
l. Explain the concept of pseudo nMOS ROM with the help of neat diagram.
m. Explain the concept of 1 transistor DRAM cell. Also, draw the DRAM sub-array.
n. Explain the concept of Dual edge registers.
o. Write a note on:
i. Mesochronous interconnect ii. Plesiochronous interconnect

Q. 4. Solve the following: [2 X 6 = 12 Marks]

a. Classify timings depending on local clock.

b. Explain the concept of Bistability with the help of neat diagrams. Also, explain
metastability.
c. Explain how negative and positive level latches can be designed using multiplexers.
d. Explain C2MOS and TSPCR approach for skew tolerant.
e. Explain various clock distribution techniques.
f. Explain the concept of clock skew and clock jitter. What are the various sources of
Clock skew and clock jitter?
g. Explain the concept of clock distribution. What are the techniques to reduce clock
skew and clock jitter?
h. Explain the concept of CLA adder with the help of equations.
i. Explain the concept of 6 transistor SRAM cell. Also, explain read and write
operation using this memory cell.