RAJALAKSHMI ENGINEERING COLLEGE, THANDALAM

EC19641- VLSI DESIGN

QUESTION BANK-PART B

UNIT 1
1. Derive the drain to source current for three different regions of MOS transistor
2. Explain in detail about n-well fabrication process of complementary MOS transistor.
3. List out the layout design rules. Draw the layout and stick diagram of CMOS basic logic
gates( Inverter, 2-input NAND,NOR, 3-input NAND, NOR, 4-input NAND and NOR),
4. Explain the voltage transfer characteristics of CMOS inverter for different input
conditions and also explain Noise margin.
5. Explain the DC transfer characteristics of a CMOS inverter with necessary conditions for
the different regions of operation.
6. Explain Ideal I-V characteristics of MOS transistor.
7. Explain C-V characteristics of MOS transistor with neat diagrams.
8. Calculate the minimum delay of the path from A to B in the figure shown below and
choose the transistor sizes to achieve this delay. The initial NAND2 may present a load of
8 λ of transistor width on the input and the output load is equivalent to 45 λ of transistor
width.

9. Explain Non-ideal IV characteristics of MOSFET.

10. Explain Logical Effort and Parasitic delay.

UNIT 2
1. Draw the static CMOS logic circuit for the Boolean expressions given in the notes.
2. Explain static CMOS design of Ratioed logic.
3. Explain pseudo-NMOS logic with an example.
4. Explain the domino logic and Dual rail domino logic with neat diagram.
5. Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expressions.
6. Discuss in detail the characteristics of CMOS pass transistor logic and Differential
Pass Transistor Logic with an example.
 7. What are the sources of power dissipation in CMOS and discuss various design
techniques to reduce power dissipation in CMOS.( Refer Power dissipation)
8. Explain the operation of dynamic CMOS design with an example.
9. Explain the operation of Transmission gates with an example.
UNIT 3
1. Discuss in detail about static latches with a neat diagram.
2. Discuss in detail about the operation of master - slave based edge triggered register.
3. Explain about the concept of pipelining in detail to optimize sequential circuits.
4. Explain about dynamic latches and registers with a neat sketch.
5. Explain the operation of Clocked – CMOS(C2 MOS) registers.
6. Discuss in detail various pipelining approaches to optimize sequential circuits.
7. Explain timing issues.(Clock skew and Clock jitter).
8. Explain NORA-CMOS in detail.

UNIT 4
1. Assess the structure of Binary adder with a neat diagram and explain its operation.
2. What are the types of shifters used in arithmetic circuits? Explain any one shifter
in detail.
3. Explain Ripple Carry Adder with near diagram.
4. Design a multiplier for 4 bit by 4 bit. Explain its operation and summarize the
number of adders.
5. Explain 4x4 array multiplier with its critical path calculation.
6. Give a brief note on CMOS S-RAM cell and 1-transistor Dynamic RAM cell.
7. How the full adder circuit is implemented using static CMOS design and write the
expressions of output with inverting property.
8. Explain Barrel shifter and one-bit programmable shifter.
9. Explain the memory architectures.
UNIT 5
1. Explain the operation of Serial and Parallel scan design used in testing.
2. Draw and explain the Configurable Logic Block (CLB) and IOB of Xilinx FPGA
with neat diagrams.(Refer Xilinx 3000, 4000 series)
3. Discuss in detail about different types of ASIC with neat diagram.
4. Describe the Steps involved in ASIC design flow in detail.
5. Explain the operation of MUX based architecture of FPGA with ACT1 and ACT
2 modules.(Refer ACTEL architectures).
6. Draw and explain architecture of Array-based Altera FLEX and MAX FPGA
building block architectures.
7. What is the need for testing? Explain the DFT( Design for Testability ) of Adhoc
testing and Scan based testing.
8. Explain Full custom design and Semi custom design.