ASSIGNMENT

Course id: EC 4201

(For reading and solving only, no submission)
1. Describe briefly NMOS fabrication process with sketches.
2. Sketch a CPL circuit that generates Z=ABC and Z  A  B  C
3. (a)Sketch the stick diagram of 2 input NOR gate in CMOS static style
(b) Draw the layout for the circuit drawn in Q # 3(a) above.
4. (a)We have a DRAM cell with Cs= 45 fF and a bitline capacitance Cbit = 250fF. It is to be
used in a system where VDD=3. 3 V and Vtn=0.55 V.
 Find the maximum amount of charge that can be stored on Cs.
 Suppose that the voltage on the capacitor is charged to a level of Vmax. The WL
controlling the access FET is dropped to a value WL = 0 at time t =0. The leakage
current is estimated to be 50 nA. To detect a logic ‘1’ state the voltage on the
bit line must be at least 1.5 V. Find the hold time.
(b) Draw the sketch of a generic SRAM cell and briefly explain each component that
that it comprises.
5. We have a DRAM cell with Cs= 50 fF and a bitline capacitance Cbit = 8 Cs. Assume a
maximum voltage of Vs= Vmax= 2. 5 V on the storage capacitor what will be the final
voltage during logic 1 operation.
6. Implement the equation X = ((A’ + B’) (C’ + D’ + E’) + F’) G’ using complementary CMOS.
Size the devices so that the output resistance is the same as that of an inverter with
an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst
and best equivalent pull-up or pull-down resistance?
7. Design a CMOS half adder circuit.
8. Suppose we wish to implement the two logic functions given by
F = A + B + C and G = A + B + C + D. Assume both true and complementary signals are
available.
 Implement these functions in dynamic CMOS as cascaded ø stages so as to
minimize the total transistor count.
 Design an np-CMOS implementation of the same logic functions.
9. Design a dynamic logic circuit whose output is OUT= A  B C
10. (a) Draw a gate array IC having three rows, the first row having four 2 input AND gates,
the second row having four 2 input OR gates, and the third row having four NOT gates.
Show how to instantiate wires to the gate array to implement the function
F(a, b, c)= abc +a1b1c1.
(b) Which of the following implementations are not possible?
 A custom processor on an FPGA
 A custom processor on an ASIC
 A custom processor on a full custom IC
 A programmable processor on an FPGA
 A programmable processor on an ASIC
 A programmable processor on a full custom IC
Briefly explain your answers.
11. Design a two stage compensated OPAMP to meet the following specifications.
A080 dB, GBW= 50 MHz, SR=20 V/s.

Take following data

k n/  120 A V 2 , k p'  k n' / 2 , =0.05 V-1, Cc= 5 pF., Vtn= 0.4 V, Vtp=-0.4 V.

12. Design a two stage compensated OPAMP to meet the following specifications.
A020,000, GBW= 5 MHz, SR=10 V/s

Take following data

k n/  25 A V 2 , k p'  k n' / 2 , =0.01 V-1, Cc= 5 pF.

13. Design static CMOS gates that have the following outputs. Assume both true and
complementary variables are available.
F=ABC +BD; F=AB + A’C +BC; F= (A+ B+ CD)’ +A
14. Implement F=(AB+CD)’ as a single stage complementary CMOS gate and pseudo
NMOS gate.
15. Sketch complete circuit for C2MOS master-slave D flip-flop.