Homework Assignment #4

Total: 120pts.
Due 5:30pm, Monday, Aprial 27, 2012
Q1) Consider the 0.25-micron CMOS technology used in the Lab for a pseudo-NMOS
circuit implementation of the logic function F = (A + BC’)’. The device sizes are as
follows: PMOS W=2.0μm, L=7μm and NMOS W=2.0μm, L=1.2μm, for all NMOS
devices, respectively. Assume that CL = 20fF and VDD = 2.5V. Work with the parameters
given in Table 3-2 on Page 103 of the Text.
Tasks:
a) Obtain analytically the worst case VOL (i.e., the highest). (12 pts.)
b) Calculate the static power consumption for this circuit. (8 pts.)
c) Obtain analytically tPLH and the worst case tPHL, respectively, using the method
learned in class. (30 pts.)

Q2). Consider the 0.25-micron complementary static CMOS technology used in the
Lab for the complex gate implementing F = A + B'C. Uniform device sizes are as
follows: PMOS W=5.0μm, L=1.2μm and NMOS W=2.0μm, L=1.2μm, respectively.
Assume that CL = 10.0fF and VDD = 2.5V.
Calculate the dynamic power consumption for this gate. Assume that the input signals'
change rate is 200MHz and the probabilities of the input high-levels are PA=0.4, PB=0.5
and PC=0.6, respectively. (10 pts.)
2. Consider the function F = A’∙C + D∙B’ using transmission gates (CMOS pass-
transistor technology). Output signal F should be driven by a complementary CMOS
inverter. You may assume that both complemented and un-complemented signals are
available. Model the circuit using Design Architect and simulate its performance using
LTspice and Electric. Turn in a printout of the circuit diagram and the simulation results,
respectively, along with your comments. No layout is needed.
Tasks:
a) Verify the correct operation of your circuit by simulation. (50 pts.)
b) Obtain tPHL, and tPLH through simulation. Use a 10fF capacitor as a load device.
(10 pts.)
You are to turn in hard copies of your circuit diagram, and simulation results,
respectively. Comment on your results.