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EHB 322E Digital Electronic Circuits Final Exam

1- Determine whether the statement is true or false

1 correct answer is worth 1 pts and 1 wrong answer is worth -1

Ratio of the channel width of the input transistor to channel width of the load transistor in a
Pseudo NMOS gate should be increased in order to bring VOL value closer to ground.
The maximum frequency of an signal to a logic gate which can be processed properly is
determined by the minimum delay for high to low and low to high transitions.
The area of a logic gate cannot be changed in layout once its schematic design is completed.
Different interconnect lengths to different parts of a synchronous circuit is one factor that causes
clock signals to arrive at different parts of the circuit at different times.
Circuits which rely on charge stored on floating nodes and cannot wait long periods of wait time
in a given state due to leakage from floating nodes are called dynamic circuits.
PMOS dynamic Gates operate slower than NMOS dynamic Gates (transistors are same size)
due to smaller mobility of holes.
CMOS lojic is generally used in PLA structures due to its compact pull-up network.
Large scale Rom structures are built with NAND Gates since VOL of NOR based structures are
higher than NAND structures.
EPROM and EEPROM structures are built with duaal gate transistors. One of the Gates is a
floating gate.
The advantage of static RAM is small area while dynamic RAM are faster.

2- VDD= 5 V, nCox=60 A/V2, pCox=20 A/V2,

VTN=0.6 V, VTP= -0.6 V, Lmin= 0.35 m,
λn=0.1 V-1, λp=0.1 V-1
(20Puan)

a) Determine the Logic function Z in terms of A,

B, C, D ad E.

b) All transistors in the circuit are minimum size.

Equivalent capasitance at node X (Cx) is 0.5pF.
Determine the worst case PHL at node X.

c) All inputs to NMOS dynamic gate (A, B, C, φ) are set to VDD/2. If you wish to set the output at X
to VDD/2, what should the channel width of the pull up transistor be?
Hint: Use the equivalent Inverter. Drain currents of NMOS and PMOS must be equal.

  V 
2

SAT: I D   VGS  VTH  1   V  I D   VGS  VTH VDS

2 DS
DS Triode:
2
  CoxW L
CL 1  2VTN 3V  4VTN 
TPHL    ln DD  W1
N V DD  VTN V 
 DD  VTN V DD  W2 PSEUDO
CL 1   2VTP 3V  4VTP  W3 NMOS ROM
TPLH    ln DD 
P V DD  VTP  V DD  VTP V DD  W4

3- When the first row (W 1=1) of the Pseudo NMOS ROM is read with
the column decoder, the output is given by the logic function
___ ___ ___ ___ ___ ___ COLUMN
Y  X1  X 2  X 3  X1  X 2  X 3  X1 X 2  X 3 MUX
Draw the first row of the ROM and the column decoder circuit.
(20Puan)
S4- Flip-flops in the circuit are identical. setup time for FF is 25ps, clock to Q propagation delay is
30 ps and hold time is 0 ps. Delay of first logic block is 150 ps and delay of second logic block is
200 ps. Delay of the inverter generating the inverted clock for FF2 is 10 ps.
Remember that inputs to FF must be ready a sufficient time before the clock edge arrives.
Otherwise, the FF cannot store the correct input. (20 Puan)
a) Calculate minimum clock period if
CLK signal has 50% duty cycle.
D Q Logic 1 D Q Logic 2
b) Calculate minimum clock period if
CLK
high and low levels of the clock can
be set independently.

5- VDD=1.2V, Cox =12 fF/µm2, µn = 0.051 m2.V-1.s-1, µp= 0.017 m2.V-1.s-1, VTHN = 0.2V, VTHP = -0.2V,
Lmin = 0.12µm, Wmin = 0.18µm
All transistors have minimum channel length. NMOS transistors in the circuit are minimum size.
PMOS and NMOS transistors have equal µCox(W/L).
Treat all transistors as a constant resistance for delay calculations. Assume capacitance at gate,
source and drain terminals of a transistor are equal and given by CoxWL. Serial NMOS and serial
PMOS transistors share a single diffusion region as their source/drain. (30
Puan)
P1 P3
If both the output node and an intermediate node
U Y
will be charged/discharged, intermediate node φ1 φ2 Q P5
will increase the delay (Use Elmore delay model). P2 P4
D X Qb
If an intermediate node is already charged to its
final value, ignore the intermediate node N2 N4
φ1 φ2 N5
capacitance in delay calculation. V Z
N1 N3
a) What is type of digital circuit is the circuit in
figure?
b) Calculate total parasitic capacitance at nodes, U, V, X, Y, Z and Q. φ2
c) Assume D=1. Describe what happens at all labeled nodes if CLK is
initially low, then it goes high and then goes low again. φ1
d) What would happen if N2 and P2 turned on before N4 and P4 were
CLK
completely off?
e) Assume D was 0 for at least 2 clock periods then it switched to 1 while φ 1
is high. How long will it take for X to cross VDD/2?
Assume the propagation delay while charging/ discharging a weak zero/ weak one is the
same as a strong zero/ strong one.
f) How long will it take new value of X to progress to Q after φ2 is switched high.

1  PHL  R DOWN C L ln 2   PLH  RUP C L ln 2 

RON 
C ox W L V DD  VTH 

ELMORE DELAY AT OUTPUT

 P  R1C1  R1  R2 C2 ln2 R1 R2 OUT
+

Vs
C1 C2
1)
a) PMOS transistor (load) is always ON in a pseudo NMOS gate. The NMOS (input or driver) must be
stronger than PMOS to pull the output low. Stronger NMOS and Weaker PMOS will result in a
lower VOL voltage. Statement is TRUE.

b) Low and high levels of the input signal should be enough for the output to rise or fall to the new
logic level. Therefore, the minimum clock frequency is the sum of worst case tPHL and tPLH.
Statement is FALSE.

c) Area can be decreased with proper layout. Statement is FALSE

d) Length of the interconnect increases both the resistance and the parasitic capacitance of interconnect.
Therefore, a longer interconnect will increase the delay. Statement is TRUE.

e) Statement is TRUE.

f) PMOS transistors have to be larger to achieve the same effective drain current.Therefore, the
parasitic capacitance of a PMOS type gate is much larger than NMOS type gate with same pulling
power. Statement is TRUE.

g) Q of an N-input CMOS NOR gate will have N PMOS transistors each will be much larger than
NMOS transistors. It is not practicle to use CMOS NOR gate in a PLA array. Statement is FALSE.

h) Pulldown network of a NOR gate has several parallel NMOS transistors. Since there is a single
transistor in each chain, VOL can be minimal. Statement is FALSE.

i) Floating gate transistors are used for Non-Volatile memories. The threshold voltage of these
transistors change by tunneling electrons to floating gate. Statement is TRUE.

j) Dynamic RAM occupy much smaller area, but they require special manufacturing processes and
periodic refreshing. Statement is FALSE.
 _____________
 __ __  __
2) a) X  A  B  C   A B   C
 
 __ __
 __ _____________
Y   D E   X  D  E  X
 
__ _____________
 __ __  __
Z  Y  D  E  A  B  C  D  E   A B   C
 
b) Worst Case scenario for NMOS Dynamic Gate: A&B on, C off
3 serial NMOS:
1
W   L   L   L   Wmin 1
             
 L eq  W  A  W  B  W  Foot  3Lmin 3
CL 1  2VTN 3V  4VTN 
TPHL    ln DD 
 N Cox W L  N VDD  VTN  VDD  VTN VDD 
5 1013 1  2  0.6  3  5   4  0.6  
TPHL    ln   6.80ns
60 10  1 3 5  0.6  5  0.6
6
5 
1
L   L   L   1  W   L
c)                 
 W eq   W  A  W  B   L C   W  Foot
1
L  2 L 1 W  L 5
        min 
min min

 W eq  Wmin  Lmin 


Wmin 3

I D   N Cox W L  N VGSN  VTHN  1  NVDSN 

2

I D   P Cox W L  P  VGSP  VTHP  1   

2
P VDSP
2
W  V   VDD 
I D   N Cox    DD  VTHN   1  N 
 L N  2   2 
  V 
2
W   V 
I D   P Cox    VDD  DD  VTHP  1  P VDD  DD  
 L P  2    2 
1 W 
I D  60 106     2.5  0.6  1  0.1 2.5    20 10 6     5  2.5  0.6  1  0.1 5  2.5  
2 2

3  L P
W  60 106   3 5 9
   
 L P 20 106 5
3) First row of the Rom

W1

C0 C1 C2 C3 C4 C5 C6 C7

AND-OR based MUX

B0

B1

B2

B3

B4

B5

B6

B7

C0 C1 C2 C3 C4 C5 C6 C7

X3 X2 X1 8 x (AND4) gates OR8

B0=X1+X2+X3+C0=X1*X2*X3*C0 B1=X1+X2+X3+C0=X1*X2*X3*C1 Y

B2=X1+X2+X3+C0=X1*X2*X3*C3 B3=X1+X2+X3+C0=X1*X2*X3*C3 Y=B0+B1+B2+B3+B4+B5+B6+B7

Tree MUX

C0 C1 C2 C3 C4 C5 C6 C7

X1

X2

X3

MUX with decoder:

C0 C1 C2 C3 C4 C5 C6 C7

B0

B1

B2

B3

B4

B5

B6

B7

Y
Decoder NMOS
X3 X2 X1 Switch Array
4) Input of Logic 1 will be available 30ps after CLK rising edge. Output of Logic 1 will be available 150ps
after this instance (170ps after CLK rising edge). This instance must be at least 25 ps (setup time) before
arrival of Clock input of second FF. Clock input of second FF will arrive 10ps after CLK falling edge due
to inverter delay.
Input of Logic 2 will be available 30ps after clock input of second FF, this is 40ps after the falling edge of
CLK. Output of Logic 2 is available 200ps later (240 ps after CLK falling edge). This output is input of first
FF, so it should arrive at least 25 ps (setup time) befor CLK rising edge.
Minimum time difference required between clock edges of 1st and 2nd FFs:
t1  30 ps  150 ps  25 ps  205 ps
Minimum time difference required between rising edge and falling edge of CLK is:
t high  30 ps  150 ps  25 ps  10 ps  195 ps
Minimum time difference required between clock edges of 2nd and 1st FFs:
t2  30 ps  200 ps  25 ps  255 ps
Minimum time difference required between falling edge and rising edge of CLK is:
t low  10 ps  30 ps  200 ps  25 ps  265 ps
a) If Duty cycle is 50%, TCLK,min=2x265ps=530ps
b) If Duty cycle is not 50%, TCLK,min=195+265ps=460ps

5)
a) The circuit is a dynamic flip flop.

b) Drain of P1 and Source of P2 are connected to node U. They share 1 diffusion region. Wp=3Wmin.
We assume diffusion capacitance is equal to gate capacitance.
CU  3CoxWmin Lmin  0.7776 fF
Node Y is identical to Node U.
CY  3CoxWmin Lmin  0.7776 fF
Drain of N1 and Source of N2 are connected to node V. They share 1 diffusion region. Wn=Wmin. We
assume diffusion capacitance is equal to gate capacitance.
CV  CoxWmin Lmin  0.2592 fF
Node Z is identical to Node V.
CZ  CoxWmin Lmin  0.2592 fF
Drains of N2 and P2 and gates of N3 and P3 are connected to node X.
C X  3CoxWmin Lmin  CoxWmin Lmin  3CoxWmin Lmin  CoxWmin Lmin  8CoxWmin Lmin  2.0736 fF
Drains of N4 and P4 and gates of N5 and P5 are connected to Q.
COUT  3CoxWmin Lmin  CoxWmin Lmin  3CoxWmin Lmin  CoxWmin Lmin  8CoxWmin Lmin  2.0736 fF

c) φ1 is high and φ2 is low when CLK is low. P1 is off, N1, N2, P2 are all on. Nodes V and X are at
ground potential. Node U is a weak zero (|VTHP|).
N3, P4 and N4 are off. Z and Q remember their previous values. Y is at VDD.
When CLK switches to High, N2 and P2 turn off. U and X will remember their values (low) at the moment
φ1 switched to low.
N4 and P4 will turn on after N2 and P2 turn off (φ2 switches to high). Q will be charged to VDD and Z will be
charged to a weak 1.
Q takes the value of D at the falling edge of φ1 which corresponds to rising edge of CLK.
When CLK becomes low again, N2 and P2 turns on and inverse of the new value of D will proceed to X and
to Y or Z depending on X value, but Q will remain unchanged since P4 and N4 is off. Q does not change
until the next rising CLK edge.
d) Normally, new value of D which is taken in when N2 and P2 turn on should progress to U, V, X and
Y or Z, but not to Q. Thus, N4 and P4 must be completely off before new D is taken in. Otherwise, new
value of D might affect the value stored in Q.

e) If D was 0 for 2 clock periods,

Assume D was 0 for at least 2 clock periods, U and X are 1, V is weak 1. Q and Z are 0 and Y is weak 0. If
D switches to 1 while CLK is low, X and V will discharge to 0 and U will discharge to weak 0.
 PHL  R N 1CV  R N 1  R N 2 C X ln 2 
1
RN1  RN 2   1089
0.051  12  10  0.18 0.12  1.2  0.2
3

CV  CoxWmin Lmin  12  10 3  0.18  0.12  0.2592 fF

C X  8CoxWmin Lmin  8  12  10 3  0.18  0.12  2.0736 fF
 PHL  R N 1CV  R N 1  R N 2 C X ln 2   3.327 ps

f) How long will it take new value of X to progress to Q after φ2 is switched high.
When X switches from 1 to 0, Node Y charges to VDD. Since CY is already charged to VDD, we won’t
charge it. So, it will not contribute to delay.
1
RP3  RP 4   1089
0.017  12  10  0.54 0.12  1.2  0.2
3

CY  3CoxWmin Lmin  3  12  10 3  0.18  0.12  0.7776 fF

COUT  8CoxWmin Lmin  8  12  10 3  0.18  0.12  2.0736 fF
 PLH  R P 3  R P 4 C OUT ln 2   3.131 ps