Combinational Logic Gates in CMOS

References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
Adapted from: EE216A Lecture Notes by Prof. K. Bult ©
UCLA
 Ratioed Logic

Reduce the number of devices over complementary logic

 Ratioed Logic

• Use PDN to implement the function (which is the

negation of the network)
• Total number of devices: n for the input, 1 for the
static load
• Minimum load is 1 unit-gate load
• Functional sizing is required to optimize noise margin
 Trade-offs to be Considered

• To reduce static power, ILoad should be low

• To obtain a reasonable NML, VOL = ILoadRPDN should
be low
• To reduce tpLH CLVDD/(2ILoad), ILoad should be high
• To reduce tpHL 0.69 RPDNCL, RPDN should be kept
small
 Improving DC and AC Characteristics

• Bias circuit to force VOL below threshold

• Build better load to improve VOL and switching time
• Use differential logic to eliminate static current
Forcing the Voltage Output Low
Adaptive Load
 Improved Loads

Differential Cascade Voltage Switch Logic (DCVSL)

Example
Pass Transistor Logic
 Pass-Transistor Logic

B
A
Switch
Network B
B

• Reduced number of transistors

• No static power consumption
 Pass Transistor Logic

Control Signal
P

Pass
Signal

V F = Product Term

Z if P 0
F
V if P 1
 Basic Pass Transistor Logic Model

Control Signals
Pi

Pass F = Sum of Products

Vi
Signals

F P1 (V1 ) P2 (V 2 )  Pn (V n )
XNOR Gate
Truth Table

A B OUT Pass Function

0 0 1 -A + -B
0 1 0 A + -B
1 0 0 -A + B
1 1 1 A+ B

Modified Karnaugh Map

A
0 1

-A -A
0
-B B
B
A A
1
-B B
Boolean Function Unit

Operation P1 P2 P3 P4

AND(A,B) 0 0 0 1

XOR(A,B) 0 1 1 0

OR(A,B) 0 1 1 1

NOR(A,B) 1 0 0 0

NAND(A,B) 1 1 1 0
 NMOS-only switch

Problem: VB does not pull up to VDD, only to VDD - Vtn(body-effect)

Cannot completely turn off the PMOS transistor

Causes static power consumption
Solution 1: Transmission Gate
 Transmission Gate Implementation

A -A B -B

A -A B -B

P1
P2 F(A,B)
P3
P4 F(A,B)

B P1
P2
P3
P4
-B
Transmission Gate XNOR

-B

OUT
-A

A
 Transmission Gate (Inverting) Multiplexer

S S
VDD

V DD
S

A
M2

S F

M1

GND
In1 S S In2
Transmission Gate XOR
Resistance of Transmission Gate

B is discharged originally

For NMOS, VGS = VDS, saturated or cutoff

For PMOS, VGS = -VDD, VDS increases from

-VDD to 0, starts out in saturation, then
transitions into non-saturation

V out V tp : NMOS saturated, PMOS saturated

V tp V out V DD V tn :
NMOS saturated, PMOS linear

V DD V tn V out :

NMOS cutoff, PMOS linear

Resistance of Transmission Gate

Vout
 Approximations
• Assume both in linear region, ignore body effect
1
G eq
R eq

n
(V DD VB V tn )(V A VB ) p
(V DD V tp )(V A VB )
(V A VB ) (V A VB )

n
(V DD V tn ) p
(V DD V tp )

• Assume both in saturated region

In Ip
G eq
V DD
2 2
n
(V DD V tn ) p
(V DD V tp )
2V DD
 When Output Closely follows Input

pmost nmost
Region A: Ron
NMOS unsaturated, PMOS off

Region B:
NMOS unsaturated, PMOS unsaturated

Region C: Transmission gate

NMOS off, PMOS unsaturated

Vin
Delay in Transmission Gate Networks

Distributed RC network
 Elmore Delay

To solve for actual delay

dV i ( t ) 1
Vi 1 (t ) Vi 1 (t ) 2V i ( t )
dt R eq C

Estimate the dominant time constant:

assume all internal nodes are pre-charged to VDD,
and a step input is applied
N N N N
n(n 1)
N
C R eq R eq C R eq C
k 1 j k k 1 j k 2
 Delay Optimization by Buffer Insertion

n(n 1)
• Delay of RC chain t p 0 . 69 N
0 . 69 R eq C
2
• Delay of buffered chain
n m (m 1) n
tp 0 . 69 R eq C 1 t pbuf
m 2 m
n(m 1) n
0 . 69 R eq C 1 t pbuf
2 m

t pbuf
m opt 1 .7
R eq C
 Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S S u m G en eration
A A P Ci

A P VDD
B B
VDD A
P
P C o C arry G en eration
Ci Ci Ci
A
S etu p P
 Adder Truth Table
C A B A.B(G) A+B A + B(P) SUM CARRY
0 0 0 0 0 0 0 0
0 0 1 0 1 1 1 0
0 1 0 0 1 1 1 0
0 1 1 1 1 0 0 1
1 0 0 0 0 0 1 0
1 0 1 0 1 1 0 1
1 1 0 0 1 1 0 1
1 1 1 1 1 0 1 1

SUM = A + B + C
CARRY = C if A + B = 1
CARRY = A (or B) if A + B = 0
 Solution 2:
Level Restoring Transistor for NMOS Only Logic

• Full Swing
• Disadvantage: More complex, larger capacitance
 Level Restoring Transistor

with
5.0 5.0
without
V o u t (V )

3.0 3.0 without

with

VX
VB
1.0 1.0

-1.00 2 4 6 -1.00 2 4 6
t (nsec) t (nsec)
(a) Output node (b) Intermediate node X
 Proper Sizing of Level Restoring Transistor

• In transient, conducting path from Mr to M3 via Mn

when A is low, B switches from low to high, and X is
high
• Mr must not be too large, otherwise, X cannot be
brought below threshold voltage, VM, of inverter, Mr
cannot be turned off
 Sizing of a Level Restorer

I 3
(V DD V tn )V A

n 2
(V B VA V tn )
2
2
(V DD VM )
r
(V DD V tp )(V DD VM )
2
 Sizing of a Level Restorer
V DD 5V
V tn V tp 0 . 75 V
VM 2 . 5V
2
(V DD VM )
I r
(V DD V tp )( V DD VM ) 7 .5 r
2
I 3
(V DD V tn )V A

r
VA 1 . 76 if M 3 and M n
are of equal size
n

VB V DD

r r
VB 3 . 87 1 . 76 0 . 75 5V
n n

n
m 1 . 55
r
 Proper Sizes of Restorer

Making the NMOS pass-transistor and

PMOS restorer the same size is reasonable
Solution 3: Single Transistor Pass Gate with VT=0

VDD

VD D
0V 5V

VD D 0V O ut

5V

W A T C H O U T F O R LE A K A G E C U RR E N T S
 Complimentary Pass Transistor Logic
A
Pas s -T ran si stor
A F
B Ne twor k
B
(a)
A I n vers e
A Pas s-T r ans is tor F
B
B Ne twor k

B B B B B B

A A A

B F = AB B F =A + B A F= A Ý

A (b )
A A

B F= A B B F =A +B A F= A Ý

A ND /N A ND O R /N O R E X O R /N E XO R
 4 Input NAND in CPL

• Total number of transistors needed = 14 (including

the final buffer)
• But AND function is simultaneously present
• tpHL = 1.05ns, tpLH = 0.45ns
Dynamic Logic
 Dynamic Logic

VDD VDD

Mp Me
O ut

In 1
CL
In 1 In 2 PUN
In 2 PDN In 3
In 3 O ut

Me Mp CL

n netw ork p netw ork

• Pre c harge
2 phas e ope ra tion:
• E valua tion
Example

• N + 2 transistors
• Ratioless
• No static power consumption
• Small Noise Margins (NML)
• Requires Clock
• Pull-down resistance increases
due to the evaluation transistor
 Transient Response

6.0

Vout

4.0
EVALUATION PRECHARGE
V out (V olt)

2.0

0.0
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)
 Dynamic 4 Input NAND Gate
VDD

Out

In1
In2
In3
In4

GND
 Reliability Problems — Charge Leakage

VDD

Mp
O ut

(1 ) CL
A t
V out p rech a rg e ev a lu a te
(2 )

Me

t
(a) L eak ag e so u rces (b ) E ffect o n w av efo rm s

Dynamic circuits
M in im u m C lo c krequire
F re q u e a
n cminimal clock
y: > 1 M H z rate
 Charge Sharing (redistribution)

VD D c a s e 1 ) if V out < VT n

Mp
C V = C V t + C V –V V
L DD L out a DD Tn X
O ut
or

CL C
a
V = V t – V = – -------- V –V V
A Ma out out DD C DD Tn X
X L

Ca
B= 0 Mb c a s e 2 ) if V out > VT n

C
Cb a
V = –V ----------------------
Me out DD C + C
a L
 Minimize Charge Sharing

• Keep the change in storage voltage below | Vtp |

– the output might be connected to a static inverter as in
Domino logic

Ca V tp
0 .2
CL V DD V tn

• Ca is normally smaller than CL, but if there is series

connection of NMOS transistors, internal
capacitances can be strung together and that can
increase the voltage change
 Charge Redistribution - Solutions

VDD VDD

Mp M bl Mp M bl

Out
Out

A A Ma
Ma

B Mb B Mb

Me Me

(a) S tatic bleeder (b) P recharge of internal nodes

 Clock Feedthrough

VD D

Mp c ould poten tially forw ar d

bias the diode
O ut

CL 5V
A Ma
X

Ca
B Mb ov er shoot

Cb ou t
Me
 Clock Feedthrough and Charge Sharing

output without redistribution (Ma off)

feedthrough

out
4
V (V olt)

internal node in PDN

0
0 1 2 3
t (nsec)
 Cascading Dynamic Gates

VDD VDD V

Mp Mp
In
O ut1 O ut2

O ut1
In VTn

O ut2 V

Me Me t

(a) (b)

O n ly 0 1 Tra n s itio n s a llo w e d a t in p u ts !

 Domino Logic

VDD VD D
VDD

Mp Mp
Mr
O ut1

O u t2

In 1 S tatic In verter
In 2 PDN In 4 PDN w ith L evel R estorer
In 3

Me Me
 Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1 0 transitions at input of inverter
affects the next Domino
• Static inverter increases noise immunity, increase the
size of PMOS to increase VM
• Proper sizing of inverter to drive the fan-out in optimal
way
• Add a level-restoring transistor to overcome charge
sharing and charge loss
 np-CMOS (Zipper CMOS)

VDD VD D

Mp Me
O ut1

In 1 PUN
In 2 PDN In 4
In 3 O ut2

Me Mp

O n ly 1 0 tra n s itio n s a llo w e d a t in p u ts o f P U N

Reduced noise margins: NMH = | Vtp |, NML = | Vtn |

 Full Adder Circuit

A A B A B C A

B
B C
C
-carry
-sum
C
B C
B

A A B A B C A
 np CMOS Adder

VD D VD D
VD D VDD
S1
C i1
A1 B1 B1
A1 A1
B1 Ci1
A1
B1
Ci2

VDD
VD D
VDD

Ci1 B0
A0
A0 B0 C i0 A0
A0 B0 B0
C i0
S0

C i0

C ar ry Pat h
 Manchester Carry Chain Adder

VDD
T o tal A r ea:
225 m 4 8 .6 m
0 .5
P0 P1 P2 P3 P4

M0 M1 M2 M3 M4
3 2 .5 2 1 .5 1

C i,0 1 .5 C o ,4
3 .5 3 2 .5 2 1
G0 G1 G2 G3 G4

4 3 .5 3 2 .5 2
1 .5
 Adder Truth Table
C A B A.B(G) A+B A + B(P) SUM CARRY
0 0 0 0 0 0 0 0
0 0 1 0 1 1 1 0
0 1 0 0 1 1 1 0
0 1 1 1 1 0 0 1
1 0 0 0 0 0 1 0
1 0 1 0 1 1 0 1
1 1 0 0 1 1 0 1
1 1 1 1 1 0 1 1

SUM = A + B + C = P + C
CARRY = C if P = 1
CARRY = AB if P = 0
CARRY = G + PC
CMOS Circuit Styles - Summary