VLSI DESIGN

MEL ZG621
By
Dr. Premananda B.S.
 Reference Books
• John P. Uyemura, “Introduction to VLSI Circuits and
Systems” Wiley India Edition, 2002.
• Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital
Integrated Circuits”, Tata McGraw Hill, 3rd Edition,
2012.
• Neil H. E. Weste, David Harris, and Ayan Banerjee,
“CMOS VLSI Design” 3rd/4th edition, Pearson education.
• R. Jacob Baker, Harry W Li, and David E. Boyce, “CMOS
Circuit Design, Layout and Simulation”, PHI, 2004.
• …
 CMOS Inverter
• Ideally there is no static power dissipation. VDD
• When input is fully is high or fully low, no
current path between VDD and GND exists.
• Power is dissipated as ‘Input’ transitions
from 0→1 and 1 → 0 and a momentary
current path exists between VDD and GND.
A Y
• Power is also dissipated in the charging and
discharging of gate capacitances.

GND
 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
 CMOS Inverter

A Y VDD
0 1
1 0 OFF
A=1 Y=0

ON
A Y
GND
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
NMOS Operation Summary
PMOS Operation Summary
Inverter Characteristics
CMOS Inverter VTC
 Transfer characteristic of a CMOS Inverter
• Voltage Mapping
Operating Regions & Supply Current
CMOS Inverter VTC
Impact of Sizing & Process Variations
 Signal Strengths
• Signals 1 and 0 have strengths, measures ability to sink or
source current VDD & GND Rails are the strongest 1 and 0.
• Gate can turn the switch on only if a potential difference of at
least Vt exists between the G and S.
• Strong 1: VDD and
Strong 0: GND
• Weak 1 :(~VDD - Vt) and
Weak 0 :(~GND + Vt)
Switch Model of MOS Transistor
 Review: Voltage Degradation
• Both nMOS and pMOS have voltage degradation problems:
– nMOS degrades Logic ‘1’
– pMOS degrades Logic ‘0’
 Reduced Voltage Swing
IN

Vx = VDD – Vtn

VDD = 2.5V OUT

n transistors, W/L = 0.5μ/0.25μ

p transistors, W/L = 1.5μ/0.25μ
 Spice Simulation
3.0
IN

2.0
Voltage, V

Vx

1.0

OUT
0.0
0 0.5 1.0 1.5 2.0
Time, ns
 Pass transistors in series
• The node voltages in a pass transistor chain during Logic
‘1’ transfer is as shown.

• With threshold voltage of all transistors are same, the node

voltage at the end of the pass transistor chain will become
one threshold voltage lower than VDD, regardless of
number of pass transistors in chain.
 Pass transistors driving gate of another
Pass transistors
• Node voltages during the Logic ‘1’ transfer, when each pass
transistor is driving another pass transistor is as shown.

• In designing nMOS pass transistors logic, one must never

drive a pass transistor with the output of another pass
transistor.
Pass transistors in Series/Parallel Connection
 Pass-Transistor Logic
A

A F 0 1

B 0 0 1
F
B B 1 1 0

A
B B
(a) (b)

(a) XOR function implemented with pass-transistor circuit,

(b) K-map showing derivation of the XOR function
 Pass-Transistor Logic
A X Y F
0 0 0
0 1 A
X 1 0 A
F 1 1 1
0 B AB
Y 0 B AB
1 B AB
A 1 B AB
General topology of pass-transistor B 0 AB
function generator B 1 AB
B 0 A+B
B 1 A B
K-map of 16 possible functions B B B
that can be realized B B A B
B B A B
B B B
 Transmission Gates
• To solve voltage degradation problem, use both nMOS and
pMOS, need both true and complement of control.
• TGs act as tristate buffers and bi-directional gate.
• Note that neither transistor is connected to VDD or GND.
• When S=0, both FETs are in cutoff
(TG modeled as open switch)
• When S=1, both FETs turns on
(TG modeled as closed switch)
Resistance of Transmission Gate
 Transmission-Gate Logic
• Provides both power and ground levels.
• Good design, except needs more transistors.

A Inverting multiplexer
F
S F’ = S’A’ + SB’

B
 TG as a Tristate Buffer
s
A S B
0 1 0
1 1 1
A (Vin ) B (Vout )
X 0 Z

s
Inverting tristate buffer : just add inverter

Other TG, tristate buffer electrical symbols :

s s s
A B A B
A B s
s s
2:1 MUX using Transmission Gate
 Logic Function Implementation using
Transmission Gates

B
Y=AS+BS

Y
A B S Y
A B B AB+B=A+B
A
A B A AB
S
1 B A A+B
A 0 B AB
A
A A B AB+AB=AB
A A B AB+AB=AB
A Y=A+B

A
 Two-Way Demultiplexer

A=SD
B=SD
A
D

S
Complementary Pass-Transistor Logic
(CPL)
Pass Variables

Inputs

Control f f
Variables

F F
 Derivation of CPL Logic
B
B
A 0 1 A A A A
L2 L1
0 0 1
B
B
A 1 1 0
L1 L2
XOR XNOR
(a) (b)
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
A CPL Cell
CPL Cell used as AND/NAND
B B’

Z = AB

A’

Z’ = (AB)’

B’
CPL Cell used as OR/NOR
B’ B

Z =A+B

A’

Z’ = (A + B)’

B’
CPL Cell used as XOR/XNOR
B’ B

Z = AB’ + A’B

A’

A’

Z’ = AB + A’B’

A
 CPL Logic
A A
A A
B
n1 n2

B B
n3 n4

B
C

Q Qb C
S S (a) (b)
S S
XOR/XNOR gate
Sum circuit
CPL provides an efficient implementation of XOR function
 Formal Method for PT Logic Derivation
Complementary function can be implemented from the same
circuit structure by applying complementarity principle:
Complementarity Principle: Using the same circuit topology,
with pass signals inverted, complementary logic function is
constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate
signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual:
AND-OR (and vice-versa)
NAND-NOR (and vice-versa)
XOR and XNOR are self-dual (dual to itself)
 Derivation of CPL Logic
Complementarity: AND  NAND

B
B
A 0 1 A B A B A B A B
L 2 L1
0 0 0
B B
B B
A 1 0 1
L1 L2
AND NAND OR NOR
(a) (b) (c)

Duality: AND  OR
NAND  NOR
THANK YOU