Chapter 4: Basics of Digital Electronics

Topics to be covered: Construction and working of a CMOS NOT, NAND and NOR gates.
Building blocks of digital electronic systems – logic gates, flip-flops (SR, D, T, and JK types),
MUX, DEMUX, counters (synchronous and asynchronous types), shift registers (SISO, SIPO,
PISO, PIPO types), encoders, decoders, priority encoders, comparators. Working of DAC and
ADC.

CMOS (Complementary Metal Oxide Semiconductor)

One of the most popular MOSFET technologies available today is the Complementary MOS or
CMOS technology. The term CMOS stands for “Complementary Metal Oxide Semiconductor”.
This is the dominant semiconductor technology for microprocessors, microcontroller chips,
memories like RAM, ROM, EEPROM and application specific integrated circuits (ASICs).
Today‟s computer memories, CPUs and cell phones make use of this technology due to several
advantages. This technology makes use of both P channel and N channel semiconductor devices.

The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller
power dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS circuit has
almost no static power dissipation. Power is only dissipated in case the circuit actually switches.
This allows integrating more CMOS gates on an IC than in NMOS or bipolar technology,
resulting in much better performance. Complementary Metal Oxide Semiconductor transistor
consists P-channel MOS (PMOS) and N-channel MOS (NMOS).

CMOS Transistor
NMOS
N-channel MOSFET is built on a p-type substrate with n-type source and drain diffused on it. In
NMOS, the majority carriers are electrons. When a high voltage is applied to the gate, the
NMOS will conduct. Similarly, when a low voltage is applied to the gate, NMOS will not
conduct. NMOS are considered to be faster than PMOS, since the carriers in NMOS, which are
electrons, travel twice as fast as the holes.
PMOS

P-channel MOSFET consists P-type Source and Drain diffused on an N-type substrate. Majority
carriers are holes. When a high voltage is applied to the gate, the PMOS will not conduct. When
a low voltage is applied to the gate, the PMOS will conduct. The PMOS devices are more
immune to noise than NMOS devices.

CMOS Working Principle

In CMOS technology, both N-type and P-type transistors are used to design logic functions. The
same signal which turns ON a transistor of one type is used to turn OFF a transistor of the other
type. This characteristic allows the design of logic devices using only simple switches, without
the need for a pull-up resistor.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network

between the output and the low voltage power supply rail (Vss (or) ground).
CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the
output and the higher-voltage rail (Vdd).
Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-
type MOSFET will be ON when the n-type MOSFET is OFF, and vice-versa. The networks are
arranged such that one is ON and the other OFF for any input pattern as shown in the figure
below.

CMOS Logic Gate using Pull-Up and Pull-Down Networks

CMOS NOT gate (or) CMOS Inverter

The inverter circuit is as shown in the figure below. It consists of PMOS and NMOS FET. The
input A serves as the gate voltage for both transistors.
The NMOS transistor has an input from Vss (ground) and PMOS transistor has an input from Vdd.
The terminal Y is output.

When a low-level voltage (<Vdd, ~0v) applied to the input terminal (A) of the inverter, the
NMOS is switched OFF and PMOS is switched ON. So the output becomes Vdd or the circuit is
pulled up to Vdd. So output Y=1

When a high voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS is OFF and
NMOS is switched ON so the output will be pulled down to Vss. So output Y=0

Input Logic Input Output Logic Output

<Vdd, 0 v 0 Vdd 1
Vdd 1 Vss 0

CMOS NAND Gate

The below figure shows a 2-input CMOS NAND gate. It consists of two series NMOS transistors
between Y and ground and two parallel PMOS transistors between Y and Vdd.
 Symbol and Circuit of CMOS NAND Gate

If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking the
path from Y to Ground. But at least one of the PMOS transistors will be ON, creating a path
from Y to Vdd. Hence, the output Y will be high. If both inputs are high, both of the NMOS
transistors will be ON and both of the PMOS transistors will be OFF. Hence, the output will be
logic low. The truth table of NAND logic gate given in below table.

A B Pull-Down Pull-up Output (Y)

Network Network
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

CMOS NOR Gate

A 2-input CMOS NOR gate is shown in the figure below. The NMOS transistors are in parallel
to pull the output low when either input is high. The PMOS transistors are in series to pull the
output high when both inputs are low, as given in below table. The output is never left floating.

Symbol and Circuit of CMOS NOR Gate

The truth table of NOR logic gate given in below table.

A B Pull-Down Pull-up Output (Y)

Network Network
0 0 OFF ON 1
0 1 ON OFF 0
1 0 ON OFF 0
1 1 ON OFF 0

CMOS Applications: Complementary MOS processes were widely implemented and have
fundamentally replaced NMOS and bipolar processes for nearly all digital logic applications.
The CMOS technology has been used for the following digital IC designs.

 Computer memories, CPUs

 Microprocessor designs
 Flash memory chip designing
 Used to design application specific integrated circuits (ASICs)

Building blocks of digital electronic systems

Digital electronics deals with the manipulation of numbers. This is achieved by representing
numbers in a digital form and using logic operations to provide the processing needed. To
achieve this there is a large variety of different types of logic gate and digital circuit building
blocks that can be employed.

LOGIC GATES:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can change
often, as the circuit processes data. In most logic gates, the low state is approximately zero volts
(0 V), while the high state is approximately five volts positive (+5 V).

There are seven basic logic gates: AND, OR, ExOR, NOT, NAND, NOR, and Ex-NOR.

 NOT: The NOT gate is possibly the simplest type of logic gate. It takes a single input
and inverts it. Using this logic gate or logic circuit, a logic "1" becomes logic "0" and a
logic "0" becomes logic "1".

Truth Table
A B
0 1
1 0
AND / NAND: The AND and NAND logic gates are normally viewed together because the
output of one is the inverse of the other. The basic function of this type of logic gate is the same.
AND gate, produces an output of "1" only when both inputs are "1", otherwise it produces a "0".
The NAND type of logic gate produces the inverse of this.

Truth Table
A B C
0 0 0
1 0 0
0 1 0
1 1 1

Logic AND gate symbol

Truth Table
A B C
0 0 1
1 0 1
0 1 1
1 1 0

Logic NAND gate symbol

OR / NOR: OR gates and NOR gates are another form of logic gate that form one of the basic
building blocks of digital technology. The OR gate gives a logical "1" when one of the either
inputs (or both inputs) is high.

Similarly the NOR gate is the inverse of this and goes low, "0" when one or the either inputs (or
both inputs) is high.
Truth Table
A B C
0 0 0
1 0 1
0 1 1
1 1 1

Logic OR gate symbol

 Truth Table
A B C
0 0 1
1 0 0
0 1 0
1 1 0

Logic NOR gate symbol

Exclusive OR / Exclusive NOR: An exclusive OR (or) exclusive NOR type of logic gate is
used where an output change is only required when one of the either input is high or low and not
both.

Truth Table
A B C
0 0 0
1 0 1
0 1 1
1 1 0

Logic Exclusive OR gate circuit symbol

Truth Table
A B C
0 0 1
1 0 0
0 1 0
1 1 1

Logic Exclusive NOR gate circuit symbol

 Combinational and Sequential Circuits
Combinational Circuit – Combinational circuits are defined as the time independent circuits
which do not depends upon previous inputs to generate any output are termed as combinational
circuits.

Block Diagram

1. Elementary building blocks: Logic gates

2. In this output depends only upon present input.
3. Speed is fast.
4. Easy to design.
5. There is no feedback between input and output.
6. This is time independent.
7. Used for arithmetic as well as boolean operations.
8. Combinational circuits don‟t have capability to store any state.
9. As combinational circuits don‟t have clock, they don‟t require triggering.
10. These circuits do not have any memory element.
Examples – Encoder, Decoder, Multiplexer, De-multiplexer

Sequential Circuit- Sequential circuits are those which are dependent on clock cycles and
depend on present as well as past inputs to generate any output.

Block Diagram –

1. Elementary building blocks: Flip-flops

2. In this output depends upon present as well as past input.
3. Speed is slow.
4. Design is not easy as compared to combinational circuits.
 5. There exists a feedback path between input and output.
6. This is time dependent.
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
Examples – Flip-flops, Counters

Flip-Flops

Flip flops are actually an application of logic gates. A flip flop is an electronic circuit with two
stable states that can be used to store binary data. The stored data can be changed by applying
varying inputs. Flip flops can also be considered as the most basic idea of a Random Access
Memory [RAM]. When a certain input value is given to them, they will be remembered and
executed, if the logic gates are designed correctly. A higher application of flip flops is helpful in
designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. Set-Reset Flip Flop [SR Flip Flop]

2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q‟. The diagram and truth table is shown below.
From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0—Q=1, Q’=0 This state is also called the SET state.

S=0, R=1—Q=0, Q’=1 This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the value of S.

S=0, R=0—Q & Q’ = Remember

If both the values of S and R are switched to 0, then the circuit remembers the value of S and R
in their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q‟ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided

S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R flip flop with NAND gate has four states. They are

S=1, R=0—Q=0, Q’=1 This state is also called the SET state.

S=0, R=1—Q=1, Q’=0 This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q‟ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S and R
in their previous state.
Clocked S-R Flip Flop
It is also called a Gated S-R flip flop. The problems with S-R flip flops using NOR and NAND
gates is the invalid state. This problem can be overcome by using a bi-stable SR flip-flop that can
change outputs when certain invalid states are met, regardless of the condition of either the Set or
the Reset inputs. For this, a clocked S-R flip flop is designed by adding two NAND gates to a
basic NAND Gate flip flop. The circuit diagram and truth table is shown below.

Clk S R Q State
0 X X No change Memory
1 0 0 No change Memory
1 0 1 Q=0 Reset
1 1 0 Q=1 Set
1 1 1 Invalid Not Used
In this circuit, the output is changed (i.e. the stored data is changed) only when you give an
active clock signal. Otherwise, even if the S or R is active the data will not change.

D Flip Flop
D flip flop is actually a slight modification of the clocked SR flip-flop. From the figure you can
see that the D input is connected to the S input and the complement of the D input is connected
to the R input. The D input is passed on to the flip flop when the value of CP is „1‟.

The circuit diagram and truth table is given below.

Clock D Qn+1
0 X 0
1 0 0
1 1 1
In a D flip flop, the output can be only changed at the clock edge, and if the input changes at
other times, the output will be unaffected.
The change of state of the output is dependent on the rising edge of the clock. The output (Q) is
same as the input and can only change at the rising edge of the clock.

J-K Flip-flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The input condition of J=K=1, gives an output inverting the output state. However, the outputs
are same when one tests the circuit practically.

Clk J K Qn+1
0 X X Memory
1 0 0 Memory
1 1 0 1
1 0 1 0
1 1 1 Qn (Compliment of Qn)
T Flip Flop

A T flip flops is like JK flip-flop. These are basically single input version of JK flip flops. This
modified form of JK flip-flop is obtained by connecting both inputs J and K together. This flip-
flop has only one input along with the clock input.

These flip-flops are called T flip-flops because of their ability to complement its state (i.e.)
Toggle, hence the name Toggle flip-flop.

Truth Table

Clk T Q n+1
0 X Qn(Memory)
1 0 Qn(Memory) as J=0 & K=0
1 1 Qn (Compliment of Qn) Toggling state
as J=1 & K=1

Applications of Flip-Flops: Flip-flops are basic building blocks for

1. Counters
2. Frequency Dividers
3. Shift Registers
4. Storage Registers
 Multiplexer and De-Multiplexer

Multiplexer

Multiplexer is a logic circuit that gives single output by accepting multiple data input.
Multiplexer consists of the control signal or data select input that determine which input is
connected to the output, and also to increase the amount of data that can be sent over a network
within certain time. It is also called a data selector. It is referred to as many to one circuit due to
its ability to select the single output from multiple inputs.
The figure below shows the circuit of a MUX including input, output and control signals.

It works as a multi-position switch which is digitally controlled by the control signals. Here, the
select lines determine which input will get switched to output among several inputs. As we can
see in the figure shown above that n input signal is fed to a MUX, containing m control signals.
However, only 1 data source is transmitted to output.
A relation exists between the input and select lines which is noteworthy and is given by:

2m = n
where: m is the select lines and n is the input lines

We can have several configurations of multiplexer depending on input lines and the control
signal applied to it.

Consider a 4 to 1 multiplexer that consists of 4 input signals along with 2 control signals, in
order to provide a single output.

Here, 4 input bits applied to the MUX are D0, D1, D2, D3 and the control signals are „a‟ and „b‟.
So, any data input can be transmitted to output on changing the level of the control signal.
 4:1 Multiplexer

The truth table for the multiplexer is shown below. Let us consider 4 separate cases in order to
understand the variation in output by controlling the level of control signals.

Data Select Input Input Output

Lines Selected
A b D D Z
0 0 D0 0 0
0 0 1 1
0 1 D1 0 0
0 1 1 1
1 0 D2 0 0
1 0 1 1
1 1 D3 0 0
1 1 1 1

Case 1: Consider that both the applied control signals „a‟ and „b‟ are low i.e., 0. In such a
condition due to the presence of NOT gate inputs I1 and I2 of only AND gate 1 is high. So, if the
input bit of D0 is high then the output is high and if the input of D0 is low then AND gate
generates its output as 0.
Thus, with control signal level 00 only A1 is enabled and all others get disable hence output
achieved is the reflection of data bit associated with A1.

Case 2: When control signal „a‟ is low and „b‟ is high then it causes AND gate 2 to be enabled as
I1 and I2 of A2 will be high. So, input bit D1 decides the output of A2. If D1 is high, the output
will be 1 otherwise 0.
Case 3: Now consider that level of control signal „a‟ is high and that of „b‟ is low. This enables
only AND gate 3 as inputs I1 and I2 of A3 is high in this condition. So, applied input bit D2 will
provide the desired bit at the output.

Case 4: Let us now consider the case when the level of both the applied control signals is high or
1. Then due to this only gate, A4 gets enabled while all others get disabled. Due to this, the
output will be the result of applied input D3.

Applications of Multiplexers: Multiplexers are used in various applications wherein multiple-

data need to be transmitted by using single line.

1. Communication System: A communication system has both a communication network

and a transmission system. By using a multiplexer, the efficiency of the communication
system can be increased by allowing the transmission of data, such as audio and video
data from different channels through single lines or cables.
2. Computer Memory: Multiplexers are used in computer memory to maintain a huge
amount of memory in the computers
3. Telephone Network: In telephone networks, multiple audio signals are integrated on a
single line of transmission with the help of a multiplexer.
4. Transmission from the Computer System of a Satellite: Multiplexer is used to transmit
the data signals from the computer system of a spacecraft or a satellite to the ground
system by using a GSM satellite.

Demultiplexer
De-multiplexer is also a logic device with one input and multiple output lines. It switches a
single input to several outputs. Here also control signal plays a major role by deciding the output
to which the input is to be passed. It is also known as data distributor as it allows a single input to
be distributed among multiple outputs.

DEMUX configuration is as shown below that have only one input but „m‟ control and „n‟ output
lines.

Consider a 1:4 de-multiplexer consisting of data bit D, with 2 control signals „a‟ and „b‟.
Here, Z0, Z1, Z2, Z3 are the 4 output provided by the de-multiplexer.
As already explained that for a particular value of control signal only a single AND gate is
enabled while all others get disabled.

The truth table for a 1:4 DEMUX is shown below

Data Input Output

Select Line
A B D Z0 Z1 Z2 Z3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

Applications of De-multiplexer: De multiplexers are used to connect a single source to multiple

destinations. These applications include the following:

1. Communication System: A De-multiplexer receives the output signals from the

multiplexer and at the receiver end it converts them back to the original form.
2. Arithmetic Logic Unit: The output of the ALU is fed as an input to the De-multiplexer,
and the output of the de-multiplexer is connected to a multiple register. The output of the
ALU can be stored in multiple registers.
3. Serial to Parallel Converter: This converter is used to reconstruct parallel data. In this
technique, serial data is given as an input to the De-multiplexer at a regular interval, and a
counter is attached to the de-multiplexer at the control input to detect the data signal at
the output of the de-multiplexer.
 Counters:

Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on design. They are designed with the
help of flip flops.

Counter Classification: Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter
In asynchronous counter universal clock is not used, only first flip flop is driven by main clock
and the clock input of rest of the counters is driven by output of previous flip flops. This can be
understood by following diagram-
It is evident from timing diagram that Q0 is changing as soon as the falling edge of clock pulse is
encountered, Q1 is changing when falling edge of Q0 is encountered (because Q0 is clock pulse
for second flip flop), Q2 is changing when falling edge of Q1 is encountered (because Q1 is clock
pulse for third flip flop) Q3 is changing when falling edge of Q2 is encountered (because Q2 is
clock pulse for fourth flip flop). In this way ripples are generated through Q0, Q1, Q2, Q3 hence it
is also called RIPPLE counter.

2. Synchronous Counter
Synchronous counter has one global clock which drives each flip flop so output changes in
parallel. The one advantage of synchronous counter over asynchronous counter is, it can operate
on higher frequency than asynchronous counter as it does not have cumulative delay because of
same clock is given to each flip flop.

From circuit diagram we see that

Q0 bit gives response to each falling edge of clock
Q1 is dependent on Q0,
Q2 is dependent on Q1 and Q0,
Q3 is dependent on Q2, Q1 and Q0.
 Shift Registers
Shift Registers are sequential logic circuits, capable of storage and transfer of data. They are
made up of Flip Flops which are connected in such a way that the output of one flip flop could
serve as the input of the other flip-flop, depending on the type of shift registers being created.

Types of Shift Registers:

Shift registers are categorized into types majorly by their mode of operation, either serial or
parallel. There are four (4) basic types of shift registers:

1. Serial in – Serial out Shift Register (SISO)

2. Serial in – Parallel out shift Register (SIPO)
3. Parallel in – Parallel out Shift Register (PIPO)
4. Parallel in – Serial out Shift Register (PISO)

1. Serial in - Serial out Shift Registers

Serial in – Serial out shift registers are shift registers that streams in data serially (one bit per
clock cycle) and streams out data too in the same way, one after the other.

1. At the first clock pulse, the data at “data in” will be present at the Stage A output.
2. After the second pulse stage A data is transferred to stage B output, and data at “data
in” is transferred to stage A output.
3. After the third clock pulse, stage C is replaced by stage B output; stage B is replaced
by stage A output; and stage A is replaced by data present at “data in”.
4. After the fourth clock, the data which was first present at “data in” is at stage D output.
5. The “first in” data is “first out” as it is shifted from “data in” to “data out”.

2. Serial in – Parallel out Shift Register

These types of shift registers are used for the conversion of data from serial to parallel. The data
comes in one after the other per clock cycle and can either be shifted or replaced or be read off
at each output. This means when the data is read in, each read in bit becomes available
simultaneously on their respective output line (QA to QD for the 4-bit shift register shown below).
3. Parallel in – Serial out Shift Register

For this type of shift register, the data is supplied in parallel, for example consider the 4-bit shift
register shown below.

This register can be used to store and shift a 4-bit word, with the write/shift (WS) control input
controlling the mode of operation of the shift register. When the WS control line is low (Write
Mode), data can be written and clocked in via DA to DD. To shift the data out serially, the WS
control line is brought HIGH (Shift mode), the register then shifts the data out on clock input.

4. Parallel in – Parallel out shift register

For parallel in – parallel out shift register, the output data across the parallel outputs appear
simultaneously as the input data is fed in.

The input data at each of the input pins from DA to DD are read in at the same time when the
device is clocked and at the same time, the data read in from each of the inputs is passed out at
the corresponding output (from QA to QD).
 Encoders and Decoders

Binary code of N digits can be used to store 2N distinct elements of coded information. This is
what encoders and decoders are used for. Encoders convert 2N lines of input into a code of N
bits and Decoders decode the N bits into 2N lines.

Encoders: An encoder is a combinational circuit that converts binary information in the form
of a 2N input lines into N output lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time.
As an example, let‟s consider Octal to Binary encoder. As shown in the following figure, an
octal-to-binary encoder takes 8 input lines and generates 3 output lines.

Truth Table:
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
22 21 20
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active; 010
when D2 is active and so on.
Implementation –
From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7.
Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or 7.
Hence, the Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realized with OR gates as follows:

One limitation of this encoder is that only one input can be active at any given time. If more than
one input is active, then the output is undefined. For example, if D6 and D3 are both active, then,
our output would be 111 which is the output for D7. To overcome this, we use Priority Encoders.
Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which actually
is the output for D0 active. In order to avoid this, an extra bit can be added to the output, called
the valid bit which is 0 when all inputs are 0 and 1 otherwise.
Priority Encoder –
A priority encoder is an encoder circuit in which inputs are given priorities. When more than one
input is active at the same time, the input with higher priority takes precedence and the output
corresponding to that is generated.

Let us consider the 4 to 2 priority encoder as an example.

From the truth table, we see that when all inputs are 0, our V bit or the valid bit is zero and
outputs are not used.
The x‟s in the table shows the don‟t care condition, i.e, it may either be 0 or 1. Here, D3 has
highest priority, therefore, whatever be the other inputs, when D3 is high, output has to be 11.
And D0 has the lowest priority, therefore the output would be 00 only when D0 is high and the
other input lines are low. Similarly, D2 has higher priority over D1 and D0 but lower than D3
therefore the output would be 10 only when D2 is high and D3 are low (D0 & D1 are don‟t care).
Truth Table –
D3 D2 D1 D0 X Y V
0 0 0 0 x X 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 X x 1 0 1
1 X X x 1 1 1

Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the inputs
should be high. Hence,
V = D0 + D1 + D2 + D3
Decoders: A decoder does the opposite job of an encoder. It is a combinational circuit that
converts n lines of input into 2n lines of output.
Let‟s take an example of 3-to-8 line decoder.

Truth Table –
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence, the decoder can be realized with Not and AND
gates as follows:

D0= X‟ Y‟ Z‟
D1 = X‟ Y‟ Z
D2 = X‟ Y Z‟
D3 = X‟ Y Z
D4 = X Y‟ Z‟
D5 = X Y‟ Z
D6 = X Y Z‟
D7 = X Y Z
 Comparator
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or equal
to the value at input B etc.
The digital comparator accomplishes this using several logic gates that operate on the principles
of Boolean Algebra. There are two main types of Digital Comparator available and these are.
 1. Identity Comparator – an Identity Comparator is a digital comparator with only one
output terminal for when A = B, either A = B = 1 (HIGH) or A = B = 0 (LOW)
 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater than, A > B and less
than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1,
B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the
comparison.
For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the
following three output conditions when compared to each other.
A>B A is greater than B
A=B A is equal to B
A<B A is less than B

1-bit Digital Comparator Circuit

Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
 Analog to Digital Converter

Analog to digital converter is a converter which converts the analog (continuously variable)
signal to digital signal. This is an electronic integrated circuit which directly converts the
continuous form of signal to discrete form. It can be expressed as A/D or A-to-D or A-D or
ADC. The input (analog) to this system can have any value in a range and are directly measured.
But for output (digital) of an N-bit A/D converter, it should have only 2N discrete values.

ADC Process
There are mainly two steps involved in the process of analog to digital conversion. They are

1.Sampling and Holding

2.Quantizing and Encoding
The whole ADC conversion process is shown in figure below

Sampling and Holding

In the process of Sample and hold (S/H), the continuous signal will gets sampled and freeze
(hold) the value at a steady level for a particular period of time. It is done to remove variations in
input signal which can alter the conversion process and thereby increases the accuracy. The
minimum sampling rate has to be two times the maximum data frequency of the input signal.

Quantizing and Encoding

Before understanding quantizing, we need to first understand the term Resolution used in ADC.
It is the smallest variation in analog signal that will result in a variation in the digital output. This
actually represents the quantization error.

Where, V → Reference voltage range

2N → Number of states
N → Number of bits in digital output
Quantizing: It is the process in which the reference signal is partitioned into several discrete
quanta and then the input signal is matched with the correct quantum.
Encoding: Here; for each quantum, a unique digital code will be assigned and after that the input
signal is allocated with this digital code. The process of quantizing and encoding is demonstrated
in the table below.

From the above table we can observe that only one digital value is used to represent the whole
range of voltage in an interval. Thus, an error will occur and it is called quantization error. This
is the noise introduced by the process of quantization. Here the maximum quantization error is

Types of Analog to Digital Converter

1. Successive Approximation ADC: This converter compares the input signal with the
output of an internal DAC at each successive step. It is the most expensive type.
2. Dual Slope ADC: It have high accuracy but very slow in operation.
3. Pipeline ADC: It is same as that of two step Flash ADC.
4. Delta-Sigma ADC: It has high resolution but slow due to over sampling.
5. Flash ADC: It is the fastest ADC but very expensive.
6. Other: Staircase ramp, Voltage-to-Frequency, Switched capacitor, tracking, Charge
balancing, and resolver.

Application of ADC: ADCs are used in Computers, Cell phones, Microcontrollers, Digital
signal processing, Digital storage oscilloscopes, Scientific instruments etc.
 Digital to Analog Converter (DAC)
Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal.
A DAC can reconstruct sampled data into an analog signal with precision. The digital data may
be produced from a microprocessor, Application Specific Integrated Circuit (ASIC), or Field
Programmable Gate Array (FPGA), but ultimately the data requires the conversion to an analog
signal in order to interact with the real world.

DAC using Weighted Resistors method

Figure below shows the schematic diagram of a DAC using weighted resistors. The basic
operation of DAC is the ability to add inputs that will ultimately correspond to the contributions
of the various bits of the digital input.

In the voltage domain, that is if the input signals are voltages, the addition of the binary bits can
be achieved using the inverting summing amplifier shown in the above figure.

The input resistors of the op-amp have their resistance values weighted in a binary format. When
the logic circuit receives binary 1, the switch connects the resistor to the reference voltage. When
the logic circuit receives binary 0, the switch connects the resistor to ground. All the digital input
bits are simultaneously applied to the DAC.
The DAC generates analog output voltage corresponding to the given digital data signal. For the
DAC the given digital voltage is b3 b2 b1 b0 where each bit is a binary value (0 or 1).
The output voltage produced at output side is
V0=R0/R (b3+b2/2+b1/4+b0/8) Vref