University of Asia Pacific (UAP)

Dept. of Electrical and Electronic Engineering (EEE)

EEE 222: Electrical and Electronics Engineering II Lab
Experiment No- 01
Design and Verification of RTL Logic Gates

Objective:
The objective of this experiment is:
 To build and study logic gates: AND, NOT and NAND from bipolar transistors using
the RTL logic family.
 To verify the truth table of constructed gates.

Theory and Methodology:

The resistor-transistor Logic (RTL) circuit is one of the basic logic circuits in digital logic families. It
is a bipolar saturated device. The RTL logic is popular because of its simplicity. The RTL circuit
consists of resistors at inputs and transistors at the output side. Transistors are used as switching
devices. The emitter of the transistor is connected to the ground. The collector terminals are tied
together and given to the supply through the resistor RC.
The basic circuit in RTL IC digital logic family is NOR, NAND and NOT gate. This basic circuit is
the primary building block from which all other more complex digital components are obtained.

NOT gate:
When high voltage is applied as input to the inverter which is V cc = +5V. Here, the transistor Q1
receives the required amount of potential to move into ON condition. When the transistor moves into
the ON state, the voltage at B terminal will have a path to the earth via resistor R1.
Now, the transistor will be in short-circuited condition, so that all the V cc voltage gets dropped at R1
and no voltage appears at the output terminal which is ideally ‘0’ volts.
In general, there happens some amount of voltage drop at the emitter and collector terminals which is
approximately 0.2V.
When a low voltage (0 V) is applied as input to the inverter then the transistor’s base terminal is
provided with 0 V or it is grounded. The NPN transistor will switch off because there is no base
current. As a result, there is no current flow through the transistor. Therefore, V cc will appear at
output terminal.

Figure 1: (a) NOT gate using RTL Logic Circuit (b) Truth Table and symbol
NAND gate:
When both the inputs A and B are at 0V or logic 0, it is not enough to turn on the gates of both the
transistor. So, the transistors will not conduct. Due to this, the voltage +V CC will appear at the output
Y. Hence the output is logic 1 or logic HIGH at terminal Q.
When both inputs “A” and “B” are “HIGH” then both transistors are in saturated “ON” states and a
state “LOW” appears at the output (Q). Turning any of the inputs to logic “LOW” will drive the
relative transistor to the “OFF” state and pulls the output (Q) high to VCC.

Figure 2: (a) NAND gate using RTL Logic Circuit (b) Truth Table and symbol

AND gate
In the RTL AND gate or transistor gate, when A=0v and B=0v. Then the transistors Q1 and Q2 are
off but transistor Q3 remains in ON, and the voltage at the output is LOW or 0v because of Q3 ON
and current pass through Q3 and voltage is dropped through R.
If any one of the inputs A or B is high then either Q1 or Q2 will be off and then no voltage drop
occurs at R. So Q3 will remain turn on and therefore output will be LOW.
If input A and input B both are HIGH then both transistors Q1 and Q2 will turn on and current passes
through these transistors between ground and +5v and voltage will be LOW at the collector pin of
Q1 and at the input of Q3. So Q3 will be off and no voltage drop at collector pin and output will
HIGH.

Figure 3: (a) AND gate using RTL Logic Circuit (b) Truth Table and symbol
Equipment:
1. Transistors - 3pc
2. Resistors - 5pc
3. Power Supply
4. Trainer Board
 5. Multi-meter
6. Connecting Wires

Circuit Diagram:

Figure 1: NOT gate

Figure 2: NAND gate

Figure 3: AND gate

Experimental Procedure:
a) Construct the circuit shown in (a), (b) and (c).
b) For different input combinations, find out the logical output by observing the LED and
measure the value of output voltage using DMM.
c) Verify the truth table for each gate.

Data Table:
a) Data for NOT gate:
Input Output Logical Output Voltage
1
0

b) Data for NAND gate:

Input A Input B Output Logical Output Voltage
0 0
0 1
1 0
1 1

b) Data for AND gate:

Input A Input B Output Logical Output Voltage
0 0
0 1
1 0
1 1

Discussion:
Discuss whether you have managed to achieve your desired results.