B.E.

ELECTRONICS AND COMMUNICATION ENGINEERING

CONTINUOUS INTERNAL ASSESSMENT – 1 Answer Key

Class Course Code Course Title Date

III ECE EC3552 VLSI and Chip Design 05.09.23 AN
Duration: 90 min Max:50 Marks

Part – A (10 x 02 = 20 Marks) RBT CO Marks

Answer All Questions
1 Draw the DC transfer characteristics of CMOS inverter U 1 2

Ans 2X1=2

2 What are the advantages of CMOS technology? U 1 2

• Low power consumption

• High performance
4X0.5 =2
Ans • Scalable threshold voltage
• High noise margin
• Low output drive current

3 Sketch the CMOS logic for the function F=AB+CD U 1 2

Ans 2X1=2

By what factor, gate capacitance must be scaled if constant electric U 1 2

4
field scaling is employed.

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 Scaling Factors -1
Explanation: Constant electric scaling model and constant voltage
2X1 =2
Ans scaling model is used for scaling.
Explanation: α is used as the scaling factor for linear dimensions where as
β is used for supply voltage V dd, gate oxide thickness etc.
Why the tunneling current is higher for nMos transistor than pMos U 1 2
5
transistor with silica gate?
Tunneling current is an order of magnitude higher for nMOS than pMOS
transistors with Sio2 gate dielectrics because the electrons tunnel from 2X1 =2
Ans
the conduction band while the holes tunnel from thevalence band and
see a higher barrier
6 Why NMOS device conducts strong zero and week one? AN 1 2

So the maximum voltage level that the output node can be charged to
is VDD-Vthn. So the maximum voltage level that the output node can be
2X1 =2
Ans discharged to is |Vthp|. So an NMOS passes weak 1 and PMOS passes
weak 0 whereas no such situations occur when an NMOS passes 0 and a
PMOS passes 1.
7 What is the influence of voltage scaling on power and delay? U 1 2

If the power supply voltage is scaled down while all other parameters
are kept constant, the propagation delay time would increase

Ans 2X1 =2

8 Point out the set of design rules for layouts with two metal layers. U 2 2
• Micron based design rules
In this approach, the design rules are expressed in absolute dimensions
(e.g. 0.75μm) and therefore can exploit the features of a given process
to a maximum degree.

Ans
• Lambda based design rules
In this approach, all rules are defined in terms of a single parameter
λ. The rules are so chosen that a design can be easily ported over a
cross section of industrial process ,making the layout portable

9 Draw the stick diagram of static CMOS 2 input NAND gate. U 2 2

2X1 =2

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 10 Define propagation delay of CMOS Inverter. U 2 2

• The propagation delay of a logic gate e.g. inverter is the difference

2X1 =2
Ans in time (calculated at 50% of input-output transition), when output
switches, after application of input.

Part – B (02 x 16 = 32 Marks) RBT CO Marks

Answer All Questions
11(a) Derive expressions for the drain-to-source current in the non- U 1 15
saturated and saturated regions of operation of an nMOS transistor.

Ans

The long-channel model assumes that the current through an OFF transistor
is 0. When a transistor turns ON (Vgs > Vt ), the gate attracts carriers
Total =15
(electrons) to form a chan nel. The electrons drift from source to drain at a
rate proportional to the electric field between these regions. Thus, we can
compute currents if we know the amount of charge in the channel and the
rate at which it moves. We know that the charge on each plate of a
capacitor is Q = CV. Thus, the charge in the channel Qchannel is (2.1)
where Cg is the capacitance of the gate to the channel and Vgc - Vt is the
amount of voltage attracting charge to the channel beyond the minimum
required to invert from p to n. The gate voltage is referenced to the
channel, which is not grounded. If the source is at Vs and the drain is at Vd ,
the average is Vc = (Vs + Vd )/2 = Vs + Vds /2. Therefore, the mean
difference between the gate and channel potentials Vgc is Vg – Vc = Vgs –
Vds /2

OR
11(b) Explain in detail about the non ideal I-V characteristics of a CMOS device. U 1 15

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Ans The saturation current increases less than quadratically with increasing Explanation-9
Vgs. This is caused by two effects: velocity saturation and mobility Expressions-6

degradation. At high lateral field strengths (Vds/L), carrier velocity

Total = 15
ceases to increase linearly with field strength. This is called velocity
saturation and results in lower Ids than expected at high Vds. At high
vertical field strengths (Vgs /tox ), the carriers scatter off the oxide
interface more often, slowing their progess. This mobility degradation
effect also leads to less current than expected at high Vgs. The
saturation current of the nonideal transistor increases somewhat with
Vds. This is caused by channel length modulation, in which higher Vds
increases the size of the depletion region around the drain and thus
effectively shortens the channel

12(a) Draw and explain the DC and transfer characteristics of a CMOS U 1 15

inverter with necessary conditions for the different regions of
operation.
Ans

Operation- 5
Waveform – 3
Explanation-7

OR
12(b) Discuss the principle of constant field and lateral scaling. Write the U 1 15
effects of the above scaling methods on the device characteristics.

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 In this ideal model, voltages and dimensions are scaled by the same factor
Ans S. The goal is to keep the electrical field patterns in the scaled device
identical to those in the original device. Keeping the electrical fields
constant ensures the physical integrity of the device and avoids breakdown Total=15
or other secondary effects. This scaling leads to greater device den sity
(Area), higher performance (Intrinsic Delay), and reduced power
consumption (P). We use the intrinsic time constant, which is the product of
the gate capacitance and the on-resistance, as a measure for the
performance. The analysis shows that the on-resistance remains constant
due to the simultaneous scaling of voltage swing and current level. The
performance improved is solely due to the reduced capacitance.

FACULTY IN-CHARGE HOD

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