Ex. No. 9a Date:14.07.

2021
SEQUENCE DETECTOR
Aim: To write a Verilog HDL to model a mealy fsm to detect the sequence 0101.
Hardware Requirements:
i) Desktop PC
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
A sequence detector is a sequential state machine. In a Moore machine, output depends only
on the present state and not dependent on the input (x). Hence in the diagram, the output is
written with the states. In a mealy machine, output depends both on the present state and on
the input (x).

State Diagram: (Draw the state diagram)

Program:
module seqdetetct(

input clk,

input reset,

input x,

output reg yout,

reg y

);

parameter s0 = 2'b00;

parameter s1 = 2'b01;

parameter s2 = 2'b10;

parameter s3 = 2'b11;

reg [1:0] p_s;

reg [1:0] n_s;

always@(posedge clk,posedge reset)

begin

if(reset)

begin

p_s<=s0;

yout<=1'b0;

end

else

begin

p_s<=n_s;

yout<=y;

end

end
always@(p_s,x)

begin

case(p_s)

s0:if(x)

begin

n_s<=s0;

y<=1'b0;

end

else

begin

n_s<=s1;

y<=1'b0;

end

s1:if(x)

begin

n_s<=s2;

y<=1'b0;

end

else

begin

n_s<=s1;

y<=1'b0;

end

s2:if(x)

begin

n_s<=s0;

y<=1'b0;
 end

else

begin

n_s<=s3;

y<=1'b0;

end

s3:if(x)

begin

n_s<=s2;

y<=1'b1;

end

else

begin

n_s<=s1;

y<=1'b0;

end

endcase

end

endmodule
Output:

DESIGN SUMMARY AND TIMING SUMMARY:

* Design Summary *

==================================================================
=======

Top Level Output File Name : seqdetetct.ngc

Primitive and Black Box Usage:

------------------------------

# BELS :3

# INV :1

# LUT3 :2

# FlipFlops/Latches :3

# FDC :3

# Clock Buffers :1

# BUFGP :1

# IO Buffers :4
# IBUF :2

# OBUF :2

Device utilization summary:

---------------------------

Selected Device : 6slx9csg324-3

Slice Logic Utilization:

Number of Slice Registers: 3 out of 11440 0%

Number of Slice LUTs: 3 out of 5720 0%

Number used as Logic: 3 out of 5720 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 6

Number with an unused Flip Flop: 3 out of 6 50%

Number with an unused LUT: 3 out of 6 50%

Number of fully used LUT-FF pairs: 0 out of 6 0%

Number of unique control sets: 1

IO Utilization:

Number of IOs: 5

Number of bonded IOBs: 5 out of 200 2%

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 16 6%

---------------------------

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

==================================================================
=======

Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP |3 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -3

Minimum period: 1.473ns (Maximum Frequency: 678.771MHz)

Minimum input arrival time before clock: 2.759ns

Maximum output required time after clock: 4.559ns

Maximum combinational path delay: 5.494ns

Timing Details:

---------------

All values displayed in nanoseconds (ns)

==================================================================
=======

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 1.473ns (frequency: 678.771MHz)

Total number of paths / destination ports: 4 / 2

-------------------------------------------------------------------------

Delay: 1.473ns (Levels of Logic = 1)

Source: p_s_FSM_FFd1 (FF)

Destination: yout (FF)

Source Clock: clk rising

Destination Clock: clk rising

 Data Path: p_s_FSM_FFd1 to yout

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 2 0.447 0.721 p_s_FSM_FFd1 (p_s_FSM_FFd1)

LUT3:I1->O 2 0.203 0.000 Mmux_y11 (y_OBUF)

FDC:D 0.102 yout

----------------------------------------

Total 1.473ns (0.752ns logic, 0.721ns route)

(51.0% logic, 49.0% route)

==================================================================
=======

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 6 / 6

-------------------------------------------------------------------------

Offset: 2.759ns (Levels of Logic = 2)

Source: x (PAD)

Destination: p_s_FSM_FFd2 (FF)

Destination Clock: clk rising

Data Path: x to p_s_FSM_FFd2

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 3 1.222 0.650 x_IBUF (x_IBUF)

 INV:I->O 1 0.206 0.579 p_s_FSM_FFd2-In1_INV_0 (p_s_FSM_FFd2-In)

FDC:D 0.102 p_s_FSM_FFd2

----------------------------------------

Total 2.759ns (1.530ns logic, 1.229ns route)

(55.5% logic, 44.5% route)

==================================================================
=======

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 3 / 2

-------------------------------------------------------------------------

Offset: 4.559ns (Levels of Logic = 2)

Source: p_s_FSM_FFd1 (FF)

Destination: y (PAD)

Source Clock: clk rising

Data Path: p_s_FSM_FFd1 to y

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 2 0.447 0.721 p_s_FSM_FFd1 (p_s_FSM_FFd1)

LUT3:I1->O 2 0.203 0.616 Mmux_y11 (y_OBUF)

OBUF:I->O 2.571 y_OBUF (y)

----------------------------------------

Total 4.559ns (3.221ns logic, 1.338ns route)

(70.7% logic, 29.3% route)

==================================================================
=======

Timing constraint: Default path analysis

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------

Delay: 5.494ns (Levels of Logic = 3)

Source: x (PAD)

Destination: y (PAD)

Data Path: x to y

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 3 1.222 0.879 x_IBUF (x_IBUF)

LUT3:I0->O 2 0.205 0.616 Mmux_y11 (y_OBUF)

OBUF:I->O 2.571 y_OBUF (y)

----------------------------------------

Total 5.494ns (3.998ns logic, 1.496ns route)

(72.8% logic, 27.2% route)

==================================================================
=======

Cross Clock Domains Report:

--------------------------

Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+
 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

clk | 1.473| | | |

---------------+---------+---------+---------+---------+

==================================================================
=======

Total REAL time to Xst completion: 6.00 secs

Total CPU time to Xst completion: 5.22 secs

-->

Total memory usage is 4486112 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish
Result: Thus, a mealy finite state machine was designed to detect the sequence which ends
with 0101 and its functionality was verified.

Ex. No. 9b Date:14.07.2021

NEWSPAPER VENDING MACHINE
Aim: To write a Verilog HDL for the following design specification:-
A simple digital circuit is to be designed for the coin acceptor of an electronic
newspaper vending machine. Assume that the newspaper cost 15 cents. The coin
acceptor takes only nickels and dimes. Exact change must be provided. The acceptor
does not return extra money.
Hardware Requirements:
i) Desktop PC
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
A sequence detector is a sequential state machine. In a Moore machine, output depends only
on the present state and not dependent on the input (x). Hence in the diagram, the output is
written with the states. In a mealy machine, output depends both on the present state and on
the input (x).

State Diagram: (Draw the state diagram)

Program:

module vending(

input clk,

input reset,

input x,

output reg yout,

reg y

);

parameter s0 = 2'b00;

parameter s1 = 2'b01;

parameter s2 = 2'b10;

parameter s3 = 2'b11;

reg [1:0] p_s;

reg [1:0] n_s;

always@(posedge clk,posedge reset)

begin

if(reset)

begin

p_s<=s0;

yout=1'b0;

end

else

begin

p_s<=n_s;

yout=y;
 end

end

always@(p_s,x)

begin

case(p_s)

s0:if(x)

begin

n_s<=s2;

y=1'b0;

end

else if(x==0)

begin

n_s<=s1;

y=1'b0;

end

else

begin

n_s<=s0;

y=1'b0;

end

s1:if(x)

begin

n_s<=s3;

y=1'b1;

end

else if(x==0)

begin
 n_s<=s2;

y=1'b0;

end

else

begin

n_s<=s1;

y=1'b0;

end

s2:if(x)

begin

n_s<=s3;

y=1'b1;

end

else if(x==0)

begin

n_s<=s3;

y=1'b1;

end

else

begin

n_s<=s2;

y=1'b0;

end

s3:n_s<=s0;

endcase

end

endmodule
Output:

Design and timing summary:

* Design Summary *
==================================================================
=======

Top Level Output File Name : vending.ngc

Primitive and Black Box Usage:

------------------------------
# BELS :4
# LUT2 :1
# LUT3 :3
# FlipFlops/Latches :5
# FDC :3
# LD :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :4
# IBUF :2
# OBUF :2

Device utilization summary:

---------------------------

Selected Device : 6slx9csg324-3

Slice Logic Utilization:

Number of Slice Registers: 3 out of 11440 0%
Number of Slice LUTs: 4 out of 5720 0%
Number used as Logic: 4 out of 5720 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 7
Number with an unused Flip Flop: 4 out of 7 57%
Number with an unused LUT: 3 out of 7 42%
Number of fully used LUT-FF pairs: 0 out of 7 0%
Number of unique control sets: 2

IO Utilization:
Number of IOs: 5
Number of bonded IOBs: 5 out of 200 2%
IOB Flip Flops/Latches: 2

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 16 6%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

==================================================================
=======
Timing Report

Timing Summary:
---------------
Speed Grade: -3

Minimum period: 1.540ns (Maximum Frequency: 649.540MHz)

Minimum input arrival time before clock: 2.408ns
Maximum output required time after clock: 3.648ns
Maximum combinational path delay: No path found
Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish

Result: Thus, a newspaper vending machine for the design specification wad designed and its
functionality was verified.
Ex. No. 10 Date:14.07.2021
IMPLEMENTATION OF MEMORY ELEMENTS – ROM / RAM
Aim: To write a Verilog HDL to design a 4x8 bit ROM and a 4x8 bit RAM.
Hardware Requirements: Desktop PC
Software Requirements:
i) Xilinx ISE 14.7
ii)ISim Simulator
Theory:
ROM (Read Only Memory):
Figure 1 shows the block diagram of a 4X8-Bit ROM. This module has 2 bits address and 8
bits data. Read is the control signal used to retrieve the content of ROM.

Fig. 1 Block Diagram of ROM

RAM (Random Acccess Memory):
Figure 2 shows a RAM of dimension 4 x 8. This module has 2 bits address, 8 bit data input
and 8 bits data outputs. Read control signal used to retrieve the content of RAM. Similarly
with the help of Write control signal data is stored in the RAM.

Fig.2 Block Diagram of RAM

Program for ROM:

module rom(

input [1:0] addr,

input cs,

output reg [7:0] out

);

reg [7:0]data[0:3];

always@(negedge cs)

begin

data[0]<=8'b01010101;

data[1]<=8'b00000000;

data[2]<=8'b11111111;

data[3]<=8'b10010010;

out <= data[addr];

end

endmodule

Output:

Design and timing summary:

 Design Summary *

=================================================================
========

Top Level Output File Name : rom.ngc

Primitive and Black Box Usage:

------------------------------

# BELS :3

# INV :1

# LUT2 :2

# FlipFlops/Latches :8

# FD_1 :8

# Clock Buffers :1

# BUFGP :1

# IO Buffers : 10

# IBUF :2

# OBUF :8

Device utilization summary:

---------------------------

Selected Device : 6slx9csg324-3

Slice Logic Utilization:

Number of Slice LUTs: 3 out of 5720 0%

 Number used as Logic: 3 out of 5720 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 3

Number with an unused Flip Flop: 3 out of 3 100%

Number with an unused LUT: 0 out of 3 0%

Number of fully used LUT-FF pairs: 0 out of 3 0%

Number of unique control sets: 1

IO Utilization:

Number of IOs: 11

Number of bonded IOBs: 11 out of 200 5%

IOB Flip Flops/Latches: 8

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 16 6%

---------------------------

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------
=================================================================
========

Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

cs | BUFGP |8 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: 2.831ns

Maximum output required time after clock: 3.597ns

 Maximum combinational path delay: No path found

Timing Details:

---------------

All values displayed in nanoseconds (ns)

=================================================================
========

Timing constraint: Default OFFSET IN BEFORE for Clock 'cs'

Total number of paths / destination ports: 11 / 8

-------------------------------------------------------------------------

Offset: 2.831ns (Levels of Logic = 2)

Source: addr<0> (PAD)

Destination: out_0 (FF)

Destination Clock: cs falling

Data Path: addr<0> to out_0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 3 1.222 0.650 addr_0_IBUF (addr_0_IBUF)

INV:I->O 3 0.206 0.650 Mram_addr[1]_data[3]

[7]_wide_mux_1_OUT1_INV_0 (Mram_addr[1]_data[3][7]_wide_mux_1_OUT)

FD_1:D 0.102 out_0

----------------------------------------

Total 2.831ns (1.530ns logic, 1.300ns route)

(54.1% logic, 45.9% route)

=================================================================
========

Timing constraint: Default OFFSET OUT AFTER for Clock 'cs'

Total number of paths / destination ports: 8 / 8

-------------------------------------------------------------------------

Offset: 3.597ns (Levels of Logic = 1)

Source: out_1_1 (FF)

Destination: out<7> (PAD)

Source Clock: cs falling

Data Path: out_1_1 to out<7>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FD_1:C->Q 1 0.447 0.579 out_1_1 (out_1_1)

OBUF:I->O 2.571 out_7_OBUF (out<7>)

----------------------------------------

Total 3.597ns (3.018ns logic, 0.579ns route)

(83.9% logic, 16.1% route)

=================================================================
========

Cross Clock Domains Report:

--------------------------

=================================================================
========
Total REAL time to Xst completion: 5.00 secs

Total CPU time to Xst completion: 5.17 secs

-->

Total memory usage is 4486112 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 15 ( 0 filtered)

Number of infos : 4 ( 0 filtered)

Program for RAM:

module ram(

input [1:0] addr,

input [7:0] in,

input cs,

input rw,

output reg [7:0] out

);

reg [7:0] data[0:3];

always@(negedge cs)

begin

if(rw)

data[addr]<=in;

else if(rw==0)

out<=data[addr];

else

out<=8'bz;

end

endmodule

Output:

Design and timing summary:

* Design Summary *
==================================================================
=======

Top Level Output File Name : ram.ngc

Primitive and Black Box Usage:

------------------------------
# BELS : 10
# GND :1
# INV :1
# LUT3 :8
# FlipFlops/Latches :8
# FD_1 :8
# RAMS :8
# RAM16X1S :8
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 19
# IBUF : 11
# OBUF :8

Device utilization summary:

---------------------------

Selected Device : 6slx9csg324-3

Slice Logic Utilization:

Number of Slice Registers: 8 out of 11440 0%
Number of Slice LUTs: 17 out of 5720 0%
Number used as Logic: 9 out of 5720 0%
Number used as Memory: 8 out of 1440 0%
Number used as RAM: 8
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 17
Number with an unused Flip Flop: 9 out of 17 52%
Number with an unused LUT: 0 out of 17 0%
Number of fully used LUT-FF pairs: 8 out of 17 47%
Number of unique control sets: 1

IO Utilization:
Number of IOs: 20
Number of bonded IOBs: 20 out of 200 10%

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 16 6%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

==================================================================
=======
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
cs | BUFGP | 16 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

Minimum period: 1.877ns (Maximum Frequency: 532.808MHz)

Minimum input arrival time before clock: 3.318ns
Maximum output required time after clock: 3.634ns
Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

==================================================================
=======
Timing constraint: Default period analysis for Clock 'cs'
Clock period: 1.877ns (frequency: 532.808MHz)
Total number of paths / destination ports: 16 / 8
-------------------------------------------------------------------------
Delay: 1.877ns (Levels of Logic = 1)
Source: Mram_data1 (RAM)
Destination: out_0 (FF)
Source Clock: cs falling
 Destination Clock: cs falling

Data Path: Mram_data1 to out_0

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAM16X1S:WCLK->O 1 0.990 0.580 Mram_data1 (_n0046[7:0]<0>)
LUT3:I2->O 1 0.205 0.000 Mmux_n004411 (n0044<0>)
FD_1:D 0.102 out_0
----------------------------------------
Total 1.877ns (1.297ns logic, 0.580ns route)
(69.1% logic, 30.9% route)

==================================================================
=======
Timing constraint: Default OFFSET IN BEFORE for Clock 'cs'
Total number of paths / destination ports: 56 / 40
-------------------------------------------------------------------------
Offset: 3.318ns (Levels of Logic = 3)
Source: addr<0> (PAD)
Destination: out_0 (FF)
Destination Clock: cs falling

Data Path: addr<0> to out_0

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 16 1.222 1.004 addr_0_IBUF (addr_0_IBUF)
RAM16X1S:A0->O 1 0.205 0.580 Mram_data2 (_n0046[7:0]<1>)
LUT3:I2->O 1 0.205 0.000 Mmux_n004421 (n0044<1>)
FD_1:D 0.102 out_1
----------------------------------------
Total 3.318ns (1.734ns logic, 1.584ns route)
(52.3% logic, 47.7% route)
==================================================================
=======
Timing constraint: Default OFFSET OUT AFTER for Clock 'cs'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 3.634ns (Levels of Logic = 1)
Source: out_7 (FF)
Destination: out<7> (PAD)
Source Clock: cs falling

Data Path: out_7 to out<7>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD_1:C->Q 2 0.447 0.616 out_7 (out_7)
OBUF:I->O 2.571 out_7_OBUF (out<7>)
----------------------------------------
Total 3.634ns (3.018ns logic, 0.616ns route)
(83.0% logic, 17.0% route)

==================================================================
=======

Cross Clock Domains Report:

--------------------------

Clock to Setup on destination clock cs

---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cs | | | 1.877| |
---------------+---------+---------+---------+---------+
==================================================================
=======

Total REAL time to Xst completion: 5.00 secs

Total CPU time to Xst completion: 5.13 secs

-->

Total memory usage is 4486116 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
 ii) Create a New Project in the desired location with top level source type as HDL
iii) Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv) Create New Source File
v) Select Verilog module with a preferred file name.
vi) Click Next
vii) Click Finish

Result: Thus, the memory elements ROM and RAM were design as per the given
specification.