Ex. No.

12a Date:26/7/21
IMPLEMENTATION OF SWITCH CONTROLLED LEDS ON SPARTAN 6 FPGA
Aim : To activate and deactivate the LEDS’ interfaced to Spartan 6 FPGA whenever the
slide switch gets activated and deactivated.
Software Requirements:
i) Xilinx ISE 14.7
ii) ISim Simulator
Hardware Requirements:
i) Universal Development FPGA Board
ii) 9V 1A Power Adaptor
iii) JTAG Cable
Theory:
Digital Inputs Toggle Switch:
The Universal Development Board has 16-slide switches, indicated as in Figure 1. The
switches connect to an associated pin name, as shown in Table 1. A detailed schematic
appears in Figure 1.

Figure 1. Slide Switches Connections from Spartan 6 FPGA Kit

GOWTHAM KANNA M 18EC1026

When in the UP or ON position, a switch connects logic High. When DOWN or in the OFF
position, the switch connects to ground, a logic Low. The switches typically exhibit about 2
ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry
could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor
provides nominal input protection.
FPGA Pin Connections to Slide Switches

Light Emitting Diodes:

Light Emitting Diodes (LEDs) are the most commonly used components, usually for
displaying pin’s digital states. The Universal Development Board has 16- LEDs located
above the slide switches, indicated by in Figure 2.

Figure 2. Point LED interface from Universal Development Board

The cathode of each LED connects to ground via a 220 ohm Ω resistor. To light an individual
LED, drive the associated FPGA control signal High, which is the opposite polarity from
lighting one of the 7-segment LEDs. FPGA pin connections to LEDs is shown in Table 2.

GOWTHAM KANNA M 18EC1026

FPGA Pin Connections to LEDS

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish
viii) Design the circuit with Verilog HDL
ix)Set the design as top-level module
x) Synthesize the design
xi)Create a User Constraint File by double clicking Post-Synthesis.
The circuit has been implemented but the Xilinx tools still need to know what
physical pins on the FPGA the input and output ports are mapped to. The UCF file
will give the tools for this information.
xii) Implement the design
xiii) Generate a bit file
xiv) Connect the 9V 1A Power Supply to the Spartan -6 Starter Kit
xv) Connect the JTAG cable from JTAG port on the FPGA to the PC parallel port
xvi) Switch ON the power switch on the FPGA. The Power LED will be illuminated

GOWTHAM KANNA M 18EC1026

 xvii) Open iMPACT Tool.

xviii) Double Click Boundary Scan on left pane and then Right Click right pane and select
Initialize chain.

GOWTHAM KANNA M 18EC1026

 xix) Now FPGA Board Devices will appear (XC6SLX9, XCF04S) FPGA and PROM. It
will ask for .bit file. Select.bit file.

xx) After bit file selection, right click XCLSX9 and click Program.

GOWTHAM KANNA M 18EC1026

 xxi) After Successful completion, it will display Program Succeeded.

Program:
module switchled(
output [15:0] led,
input [15:0] switch
);
assign led = switch;
endmodule

GOWTHAM KANNA M 18EC1026

OUTPUT:

DESIGN SUMMARY:
Top Level Output File Name : switchled.ngc

Primitive and Black Box Usage:

------------------------------
# IO Buffers : 32
# IBUF : 16
# OBUF : 16

Device utilization summary:

---------------------------

Selected Device : 6slx4tqg144-3

Slice Logic Utilization:

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0

IO Utilization:
Number of IOs: 32

GOWTHAM KANNA M 18EC1026

Number of bonded IOBs: 32 out of 102 31%

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 4.372ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------

GOWTHAM KANNA M 18EC1026

Delay: 4.372ns (Levels of Logic = 2)
Source: switch<15> (PAD)
Destination: led<15> (PAD)

Data Path: switch<15> to led<15>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.579 switch_15_IBUF (led_15_OBUF)
OBUF:I->O 2.571 led_15_OBUF (led<15>)
----------------------------------------
Total 4.372ns (3.793ns logic, 0.579ns route)
(86.8% logic, 13.2% route)

=========================================================================

Cross Clock Domains Report:

--------------------------

=========================================================================

Total REAL time to Xst completion: 14.00 secs

Total CPU time to Xst completion: 13.55 secs

-->

Total memory usage is 4498248 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Result : Thus the leds were controlled by activating the switches and the results were verified
by programming it on Spartan6 FPGA.

GOWTHAM KANNA M 18EC1026

Ex. No. 12b Date:26/7/21
ACTIVATION OF BUZZER ON SPARTAN 6 FPGA
Aim : To enable the continuous buzzer interfaced to Spartan 6 FPGA during the positive
edge trigger on clock.
Software Requirements:
i) Xilinx ISE 14.7
ii) ISim Simulator
Hardware Requirements:
i) Universal Development FPGA Board
ii) 9V 1A Power Adaptor
iii) JTAG Cable
Theory:
In Universal Development Board 5V continuous buzzer is used. To enable buzzer place
jumper J11 at E label mark position.

Schematic showing the buzzer section

Power Settings
Place jumper at E position in J11 to activate buzzer.
FPGA Pin Connections to Buzzer

FPGA Pin Connections to Clock Oscillator

GOWTHAM KANNA M 18EC1026

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish
viii) Design the circuit with Verilog HDL
ix)Set the design as top-level module
x) Synthesize the design
xi)Create a User Constraint File by double clicking Post-Synthesis.
The circuit has been implemented but the Xilinx tools still need to know what
physical pins on the FPGA the input and output ports are mapped to. The UCF file
will give the tools for this information.
xii) Implement the design
xiii) Generate a bit file
xiv) Connect the 9V 1A Power Supply to the Spartan -6 Starter Kit
xv) Connect the JTAG cable from JTAG port on the FPGA to the PC parallel port
xvi) Switch ON the power switch on the FPGA. The Power LED will be illuminated
xvii) Open iMPACT Tool.
xviii) Double Click Boundary Scan on left pane and then Right Click right pane and
select Initialize chain.
xix) Now FPGA Board Devices will appear (XC6SLX9, XCF04S) FPGA and
PROM. It will ask for .bit file. Select.bit file.

GOWTHAM KANNA M 18EC1026

 xx) After bit file selection, right click XCLSX9 and click Program.
xxi) After Successful completion, it will display Program Succeeded.

Program:
module buzzer(
input clk,
output reg buzzer
);
always@(posedge clk)
begin
buzzer<=1'b1;
end
endmodule

OUTPUT:

DESIGN SUMMARY:
Top Level Output File Name : buzzer.ngc

Primitive and Black Box Usage:

------------------------------
# BELS :1

GOWTHAM KANNA M 18EC1026

# VCC :1
# IO Buffers :1
# OBUF :1

Device utilization summary:

---------------------------

Selected Device : 6slx4tqg144-3

Slice Logic Utilization:

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0

IO Utilization:
Number of IOs: 2
Number of bonded IOBs: 1 out of 102 0%

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

GOWTHAM KANNA M 18EC1026

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================

Cross Clock Domains Report:

--------------------------

=========================================================================

Total REAL time to Xst completion: 9.00 secs

Total CPU time to Xst completion: 8.14 secs

-->

Total memory usage is 4498824 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

GOWTHAM KANNA M 18EC1026

Result: Thus the buzzer was activated during the positive edge transition on clock pulse and
the result was verified by programming it on Spartan6 FPGA.

Ex. No. 12c Date:26/7/21

DISPLAYING OF CHARACTERS ON SEVEN SEGMENT DISPLAY
Aim : To convert BCD to seven segment decoder and to display the numeric characters on
seven segment display by enabling all the 6- digit anode control signals on Spartan
6 FPGA.
Software Requirements:
i) Xilinx ISE 14.7
ii) ISim Simulator
Hardware Requirements:
i) Universal Development FPGA Board
ii) 9V 1A Power Adaptor
iii) JTAG Cable
Theory:
Seven Segment Display:
The Universal Development Board has a six-character, seven-segment LED display
controlled by FPGA user-I/O pins, as shown in Figure 1. Each digit shares eight common
control signals to light individual LED segments. Each individual character has a separate
anode control input. The pin name for each pin connected to the LED display is shown in
Table. To light an individual signal, drive the individual segment control signal Low along
with the associated anode control signal for the individual character.

GOWTHAM KANNA M 18EC1026

 Figure 1. Seven Segment Display Connections on Universal Development Board
The LED control signals are time-multiplexed to display data on all six characters, as shown
in Figure 2. Present the value to be displayed on the segment control inputs and select the
specified character by driving the associated anode control signal Low. Through persistence
of vision, the human brain perceives that all six characters appear simultaneously, similar to
the way the brain perceives a TV display. This “scanning” technique reduces the number of
I/O pins required for the six characters. In case an FPGA pin were dedicated for each
individual segment, then 48 pins are required to drive four 7-segment LED characters. The
scanning technique reduces the required I/O down to 14 pins. The drawback to this approach
is that the FPGA logic must continuously scan data out to the displays—a small price to save
36 additional I/O pins.

Figure 2. Drive Anode Input Low to Light an Individual Character

Display Characters and Resulting LED Segment Control Values
Display A B C d e f g h
Character
s
0 0 0 0 0 0 0 1 1
1 1 0 0 1 1 1 1 1

GOWTHAM KANNA M 18EC1026

2 0 0 1 0 0 1 0 1
3 0 0 0 0 1 1 0 1
4 1 0 0 1 1 0 0 1
5 0 1 0 0 1 0 0 1
6 0 1 0 0 0 0 0 1
7 0 0 0 1 1 1 1 1
8 0 0 0 0 0 0 0 1
9 0 0 0 0 1 0 0 1

Power Settings
Turn ON 7SEG DIP Switch located at SW35 to Provide 5V Supply to Seven Segment
Display.

FPGA Pin Connections to Seven Segment Display

FPGA Pin Connections to Digit Enable (Anode Control) Signals (Active High)

GOWTHAM KANNA M 18EC1026

Procedure:
i) Open Xilinx ISE 14.7 Project Navigator
ii) Create a New Project in the desired location with top level source type as HDL
iii)Device Properties window opens
Select Family - Spartan6
Device : XC6SLX9
Package : CSG324
Simulator : ISim (VHDL / Verilog)
Preferred Language : Verilog
iv)Create New Source File
v) Select Verilog module with a preferred file name.
vi)Click Next
vii) Click Finish
viii) Design the circuit with Verilog HDL
ix)Set the design as top-level module
x) Synthesize the design
xi)Create a User Constraint File by double clicking Post-Synthesis.
The circuit has been implemented but the Xilinx tools still need to know what
physical pins on the FPGA the input and output ports are mapped to. The UCF file
will give the tools for this information.
xii) Implement the design
xiii) Generate a bit file
xiv) Connect the 9V 1A Power Supply to the Spartan -6 Starter Kit
xv) Connect the JTAG cable from JTAG port on the FPGA to the PC parallel port

GOWTHAM KANNA M 18EC1026

 xvi) Switch ON the power switch on the FPGA. The Power LED will be illuminated
xvii) Open iMPACT Tool.
xviii) Double Click Boundary Scan on left pane and then Right Click right pane and
select Initialize chain.
xix) Now FPGA Board Devices will appear (XC6SLX9, XCF04S) FPGA and
PROM. It will ask for .bit file. Select.bit file.
xx) After bit file selection, right click XCLSX9 and click Program.
xxi) After Successful completion, it will display Program Succeeded.

Program:
module sevensegmentdisplay(
input [3:0] bcd,
output reg [7:0] decoder,
output [5:0] a
);
assign a = 6'b111111;
always@(bcd)
begin
case(bcd)
4'b0000:decoder=7'b00000011;
4'b0001:decoder=7'b10011111;
4'b0010:decoder=7'b00100101;
4'b0011:decoder=7'b00001101;
4'b0100:decoder=7'b11011001;
4'b0101:decoder=7'b01001001;
4'b0110:decoder=7'b01000001;
4'b0111:decoder=7'b00011111;
4'b1000:decoder=7'b00000001;
4'b1001:decoder=7'b00001001;
endcase
end
endmodule

OUTPUT:

GOWTHAM KANNA M 18EC1026

DESIGN SUMMARY:
Top Level Output File Name : sevensegmentdisplay.ngc

Primitive and Black Box Usage:

------------------------------
# BELS :9
# GND :1
# LUT3 :1
# LUT4 :6
# VCC :1
# FlipFlops/Latches :6
# LD :6
# IO Buffers : 18
# IBUF :4
# OBUF : 14

Device utilization summary:

---------------------------

Selected Device : 6slx4tqg144-3

Slice Logic Utilization:

Number of Slice LUTs: 7 out of 2400 0%
Number used as Logic: 7 out of 2400 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 7

GOWTHAM KANNA M 18EC1026

 Number with an unused Flip Flop: 7 out of 7 100%
Number with an unused LUT: 0 out of 7 0%
Number of fully used LUT-FF pairs: 0 out of 7 0%
Number of unique control sets: 1

IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 102 17%
IOB Flip Flops/Latches: 6

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0037<0>(_n0037<0>1:O) | NONE(*)(decoder_6) |6 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew
problems.

Asynchronous Control Signals Information:

----------------------------------------
No asynchronous control signals found in this design

GOWTHAM KANNA M 18EC1026

Timing Summary:
---------------
Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: 2.483ns
Maximum output required time after clock: 3.648ns
Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0037<0>'
Total number of paths / destination ports: 24 / 6
-------------------------------------------------------------------------
Offset: 2.483ns (Levels of Logic = 2)
Source: bcd<2> (PAD)
Destination: decoder_6 (LATCH)
Destination Clock: _n0037<0> falling

Data Path: bcd<2> to decoder_6

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 1.222 1.021 bcd_2_IBUF (bcd_2_IBUF)
LUT4:I0->O 1 0.203 0.000 _n0037<1>1 (_n0037<1>)
LD:D 0.037 decoder_6
----------------------------------------
Total 2.483ns (1.462ns logic, 1.021ns route)
(58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0037<0>'
Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset: 3.648ns (Levels of Logic = 1)
Source: decoder_6 (LATCH)
Destination: decoder<6> (PAD)
Source Clock: _n0037<0> falling

Data Path: decoder_6 to decoder<6>

Gate Net

GOWTHAM KANNA M 18EC1026

 Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.498 0.579 decoder_6 (decoder_6)
OBUF:I->O 2.571 decoder_6_OBUF (decoder<6>)
----------------------------------------
Total 3.648ns (3.069ns logic, 0.579ns route)
(84.1% logic, 15.9% route)

=========================================================================
Cross Clock Domains Report:
=========================================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.23 secs
-->
Total memory usage is 4498824 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 14 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

Result: Thus the characters were displayed on the seven segment led interfaced with
Spartan6 FPGA.

GOWTHAM KANNA M 18EC1026