Structure of Computer Systems – Implementing the FIFO Memory on a Development Board 1

Implementing the FIFO Memory on a Development Board

The goal of this application is to implement the FIFO memory specified in Application 6.5.12 on the
Digilent Pegasus or Spartan-3 board.

1. Adding the Control Unit

First, add a control unit to the FIFO memory specified in Application 6.5.12. This unit, named, for in-
stance, fifo_ctrl, will generate the rdptrclr, wrptrclr, rdinc, and wrinc signals. For this application, the synchro-
nous reset signals for the pointers, rdptrclr and wrptrclr, will be maintained permanently to logical 0. For each
of the rdinc and wrinc signals a positive pulse will be generated when the rd or wr signal is logical 1. In addition,
the control unit will generate the empty and full status signals. The empty signal will be set to '1' when no words
have been written into the FIFO memory, or when all the words have been read. The full signal will be set to '1'
when the FIFO memory contains 8 words that have not been read. Describe the control unit in a separate VHDL
file.

2. Adding the Components for Implementation on the Board

Next, implement the FIFO memory in the FPGA device of one of the Digilent Pegasus or Spartan-3
boards. In case of the Pegasus board, the type of the FPGA device is XC2S50 in the PQ208 package. In case of
the Spartan-3 board, the type of the FPGA device is XC3S200 in the FT256 package. For the implementation,
the buttons, slide switches, and seven-segment displays of the board will be used. Data to be written into the
memory will be entered from the SW7..SW0 slide switches (bit 8 of the memory word will not be written). The
status of the slide switches will be displayed on the two left-hand side digits of the seven-segment displays. The
rst, rd, and wr signals will be generated with the BTN2, BTN1, and BTN0 buttons, respectively. The word read
from the memory (bits 7..0 only) will be displayed on the two right-hand side digits of the seven-segment dis-
plays. The empty and full status signals will be displayed on two LEDs, for instance, LD1 and LD0. To imple-
ment the FIFO memory, perform the following steps:
1. Create a VHDL module for debouncing the buttons used to generate the rd and wr signals. The inputs
and outputs of this module, named, for instance, filtr_rdwr, are illustrated in Figure 1. When one of
these buttons is pressed, the corresponding pin of the FPGA device will be connected to logical 1. In
addition to debouncing the two buttons, this module will generate a single pulse when the correspond-
ing button is pressed. The pulse will be generated only if the button generates continuously a logical 1
signal for a certain time, e. g., during 100,000 clock cycles.
2. Add to the project the file display.vhd, containing the display module that controls the multiplexed
seven-segment displays. This file is available on the laboratory web page, in the fifo.zip archive. From
the same archive, add to the project the user constraints file to specify the connections of the I/O signals
to the pins of the FPGA device (one of the files fifo_pegasus.ucf or fifo_spartan3.ucf).
3. Create a VHDL file for a decoder of the seven-segment display. The decoder’s module, hex2sseg, has
as input the code of a hexadecimal digit (hex) and as output the vector to drive the 7 segments of the
display (sseg). The display is a common anode display, so that to turn on a segment a logical 0 signal
should be applied to that segment.
4. Create a new VHDL file for the top-level module of the FIFO memory. This module will have as inputs
the signals shown in Figure 1. Declare the components used and then instantiate these components ac-
cording to the block diagram in Figure 1.
5. In the module of the FIFO array (fifo8x9 in Figure 1), remove the logic that controls the high-
impedance state of the data_out outputs. Therefore, these outputs will always contain the word ad-
dressed by the read pointer.
2 Structure of Computer Systems – Implementing the FIFO Memory on a Development Board

Figure 1. Block diagram of the FIFO memory for implementation on a development board.

6. Compile each module and correct the possible syntactic errors.

7. Specify the use of the JTAG clock for programming the device. To perform this, in the processes win-
dow right click on the Generate Programming File line, and then select the Properties option. In the
Process Properties window select Startup Options, and for the FPGA Start-Up Clock choose the JTAG
Clock option.
8. Perform the synthesis and implementation of the design. Examine the messages displayed in the console
window and correct the errors that might occur. Often, even the warning messages may indicate that the
synthesis has not been performed correctly, due to an improper description of the circuit.
9. Generate the programming file (.bit) for the FPGA device.
10. Connect a USB or a parallel programming cable to the board and to the computer. If a parallel pro-
gramming cable has to be attached to the computer, turn off the computer or use the Hibernate function.
Connect the cable to the parallel port of the computer and to the JTAG connector of the board, and then
turn on the computer. Attention: Do not connect or disconnect the parallel programming cable when
the computer is turned on or the board is powered, because the parallel port of the computer may be
damaged.
11. When using a Pegasus board, power the board with a voltage of 3.3 V. When using a Spartan-3 board,
power the board with a voltage of 5 V.
12. If you are using a parallel programming cable, configure the FPGA device with the iMPACT tool from
the Xilinx ISE design environment. Start the iMPACT tool by expanding the line Generate Program-
ming File in the processes window and double-clicking on Configure Device (iMPACT). If you are us-
ing a USB programming cable, configure the device with the Digilent ExPort program (Start → All
Programs → Digilent → Adept → ExPort).
13. Verify the operation of the FIFO memory by writing words into the memory and by reading them.