IBERT configuration with Digilent Genesys2 Kintex FPGA Evaluation Board

Kintex7 FPGA evaluation boards can be used for BER testing of circuits from 700Mbps to 10Gbps.
This document will illustrate the configuration of the Digilent Genesys2 FPGA for a BER test.

The Genesys2 board has one High Pin Count (HPC) FPGA Mezzanine Connector. Through this
connector, we can access all eight transceivers of Quad 115 and Quad 116, and two transceivers of
Quad 117. The reference clock for these quads has to be supplied from the FMC card, via one of two
clocks that are routed to Quad 116. In Kintex FPGA's the reference clock for any GTX transceiver can
be routed to one Quad above and one Quad below internally in the FPGA. Hence, The reference clock
provided to Quad 116 can be used for Quad 115 and Quad 117.

We shall generate the IP core using Vivado 2016 version. We will use the FMC-SMA adapter card by
“hitechglobal” for this demo. For generating the referendce clock, the adapter has a one programmable
clock generator and an external clock input via SMA connectors. In this demo we will use the onboard
programmable clock generator. This generator has been programmed (using on board switches) to
generate 125MHz reference clock.

In case genesys2 board is not available in vivado you can download the board file from

https://github.com/Digilent/vivado-boards

The installation instructions can be found at

https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1

1) Start Vivado using the following commands

/cad/Xilinx_2016/Vivado/2016.1/bin/setupEnv.sh
/cad/Xilinx_2016/Vivado/2016.1/bin/vivado

Note : Replace “/cad/Xilinx_2016/Vivado” with you installation path.

2) Click start new project
Click on boards and select the board vendor as “digilentinc” and select the Genesys2 board.
Finally click finish to start the project.
3) In the Vivado window, click IP catalog and search for IBERT as shown

4) Open the IBERT core to customize the IP.

Select General ES production
In this example, we shall program all the available transceivers. Two protocols one at 2.5Gbps and one
at 5Gbps will be generated.

Note: We can use the 5Gbps protocol, drivel with alternating 1 and 0 pattern to produce a 2.5GHz
clock. This provides us with a clock to test DUT's that need a clock. In this manner we can test clocked
DUT's upto 5Gbps (by generating a 10Gbps protocol and using it to generate alternating 1 and 0
pattern).
5) In the Protocol selection tab select MGTREFCLK0 116 as the source clock for Quads 115,116 and
117. (Note Quad 118 is not connected on this Evaluation board).
Here we have selected Quad 115 and 117 to operate at 2.5Gbps and Quad 116 to operate at 5Gbps.
6) In the Clock settings tab, leave all settings as is.

7) Check the settings in the summary tab and click ok.

8) Click generate.
9) Right click on Ibert_7_seriesgtx under design sources and choose open ip example ass shown.
10) Give a new directory name and click ok.

11) A new vivado window will open up. You can close the OLD window. In the new vivado window,
click on generate bit stream. This step can take 20-25 mins to complete.

12) After the bit stream is generated, click on open Hardware manager.
13) Now its time to connect up your board. Connect the USB cable to the JTAG port. Connect the
FMC-SMA Adapter as well. Power up the FPGA board.

14) In the hardware manager click on open target and auto connect.
15) Click on program device. Select the fpga from the pop up.

16) The bit file path will be automatically loaded. Click on Program
17) SMA connectors 1 through 4 on the FMC adapter card are connected to Quad 115 and SMA
connectors 5 through 8 are connected to Quad 116. You can loop back any of the channels to check the
link.
In the TX pattern field you can choose any of PRBS generators or Fast clock or Slow clock. Fast clock
is an alternating 1 and 0 pattern. The Quad programmed for double frequency can be set to Fast clock,
and serve as a clock for the other Quads.
18) You can also create a clock sweep to plot 2D eye diagrams. Righclick on the link and click on
create sweep. I'll leave this for you to explore :)