1.

Outline a model of seven-segment decoder to display HEX digits and translate the same
into
VHDL/Verilog/SystemVerilog RTL code. Simulate the design and find errors, if any.
Observe
and show the results.
2. Sketch/draw layouts of 2-input CMOS NAND gate and 2-input CMOS NOR gate by the
direct
translation of their schematics. Perform DRC (design rule checking) on the dawn layout and
find design rule errors, if any. Simulate and observe/examine the results. Interpret the same
for
the correctness of their functionality.
3. Outline a VHDL/Verilog model and write RTL code for a Moore machine with the
following state transition diagram. Simulate/compile the same using the Xilinx development
software
(Xilinx ISE 8.1i./10.1i) and find errors, if any. Test for its operation and analyse the results.

4. Outline a VHDL/Verilog model and write RTL code for a Mealy machine with the
following state transition diagram. Simulate/compile the same using the Xilinx development
software
(Xilinx ISE 8.1i./10.1i) and find errors, if any. Test for its operation and analyse the results.

5. Write a VHDL/Verilog/SystemVerilog RTL code to develop a tri-stated buffer controlled

4channel multiplexer with each channel carrying 4 signals. Simulate/compile the same using
the Xilinx development software (Xilinx ISE 8.1i./10.1i) and find errors, if any. Test and
evaluate the obtained results.
6. Write VHDL/Verilog/SystemVerilog RTL code and develop/design an adder that adds
three 8-bit binary number. Simulate using the Xilinx development software (Xilinx ISE
8.1i./10.1i and find errors, if any, test and validate its operation.
9. Design 2-input NAND gate using SCMOS and pseudo-nMOS logic families with given
specifications with the Virtuoso ADE of Cadence and design a 2-input XOR using symbols
of 2-input SCMOS NAND gate to achieve propagation delay (tp) not longer than 20 ns and
average power consumption (Pavg) not higher than 10 μW. Simulate the designs, test and
validate your anticipation. Simulate and report the propagation delay (tp) and power
consumption (Pavg) of your XOR gate. Load the input and output of XOR gate with
singlestage NAND to make the input and output realistic.

20. Write a VHDL/Verilog/SystemVerilog model and develop a 4:1-bit multiplexer. Simulate

and synthesize the CPLD design using the Xilinx development software (Xilinx ISE 8.1i.)
and find errors, if any. Create the CPLD configuration bitstream file (*.jed), use Spartan-2
CPLD Trainer Kit and download CPLD design (using the iMPACT programming software
and the JTAG cable) onto it, demonstrate and interpret the results displayed on the kit.

21. Develop a VHDL/Verilog/SystemVerilog model and design a parameterized 4-bit parity

generator circuit. The model should provide both an odd parity and an even parity output.
Simulate and compile/synthesize the FPGA design using the Xilinx development software,
create the FPGA configuration bitstream file (*.bit), download FPGA design (using the
iMPACT programming software and the USB cable) onto the prototyping kit (use Spartan-3E
FPGA Starter Kit), test and validate its operation.

22. Write a VHDL/Verilog model and develop a 4 16 decoder. Simulate the design using the
Xilinx development software (Xilinx ISE 8.1i/10.1i) and find errors, if any. Observe/examine
the results. Interpret the same for the correctness of their functionality.

23. Outline a model of 4-bit ripple carry full adder and translate/express the same into
VHDL/Verilog RTL code. Simulate/compile the same using the Xilinx development software
(Xilinx ISE 8.1i./10.1i) and find errors, if any. Observe and show the results and explain the
same.

24. Outline a VHDL/Verilog model and write RTL code for a synchronous counter` with the
following states. Simulate/compile the same using the Xilinx Integrated Synthesis
Environment (ISE) 8.1i./10.1i) and find errors, if any. Test for its operation and analyse the
results.