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NAME OF STUDENT:
1. INTRODUCTION TO HDL 2
4. LIST OF EXPERIMENTS 8
5. VIVA QUESTION 42
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AMC Engg College,Dept Of ECE
HDL LAB
INTRODUCTION TO HDL
The designer uses HDL to describe the system in a computer language that is similar
to several commonly used Software languages, such as C.Debugging the design is easy,
HDL packages implement simulators and test benches. The two widely used hardware
description languages are VHDL and Verilog.
VHDL, which stands for Very High-Speed Integrated Circuit (VHSIC) Hardware
Description Language, was developed in early 1980s under U.S Deportment of Define
(DOD) by IBM, Texas Instruments and Intermetrics. But it was updated standardized in
1993 from IEEE. Result of this update was IEEE Slandered 1076-1987.
Verilog HDL was developed by Gateway Design Automation in 1983, then it was
improved by Cadence in 1990. Final IEEE slandered, IEEE Standard 1364-1995 was
developed in 1995 from IEEE.
Both VHDL and Verilog having different fetures, syntaxs, operator and data types.
Compared to VHDL, Verilog is easy for the, because of its les number of data type and less
number of operator availability.
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AMC Engg College,Dept Of ECE
HDL LAB
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AMC Engg College,Dept Of ECE
HDL LAB
TKBase Specifications:
1. The Clock Circuit: Connect Pin 77 to onboard 100 KHz clock oscillator.
2. Headers: There are Seven (7) 10 pin Header on TKB3S daughter board intended for use
as a GPIO. These connect to various interface header blocks on the TKBase interface card.
3. The KeyBoard Circuit: Connect Header1 on TKB2S to the keyboard matrix header
CNKey. This enables TKB2SXX to scan & read the keyboard.
4. The 8 LED’s: These 8 LED’s are used for Program status display and can be programmed
by the user. Connect any TKB3SXX Header Pins 1 through 8 to the 8 LED block Header
Marked CNLED.
5. The 4 Multiplexed 7Seg displays: the 4x7 Segment displays are multiplexed and selected
by the TKB3SXX - IO port pins Header2 marked HP2. To drive the segment’s the
TKB3SXX Header HP3 is connected to 7Segment data Header Pins CNSEG marked ‘a
thru g’.
6. The LCD interface: TKB4SXX Header4-HP4 output port pins drives the LCD data and
control line at Header marked CNLCD. Also short Control and Data header on the interface
board as we use LCD in 4 bit mode. For 8 bit mode use HP4 (Control) and HP5
(Segments).
7. The 16 bit Real Time counter: Connect XC4Sxx port pins HP5 and HP6 representing
counter pins.A0 thru A15.
8. Pattern Generator: Connect LG320 pattern generator pins 1 thru 4 to XC4Sxx port pins
44, 45, 46 and 47. The selection of input device being either LG320 or TKBase Keyboard is
done by selection bit SelPG P43.
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AMC Engg College,Dept Of ECE
HDL LAB
Steps to fallow in XILINX ISE 9.1i and VLSI trainer Kit to Execute
program and verify the result:
our project.
Select the .ucf file in the sources window, run edit constraints under the user
constraints in the process window, assign unused pin numbers to the input/output
variablessave.
Click on .vhd file, run implement design.
Run generate PROm,ACE or JTAG file, select Prepare a PROM file in the
IMPACT window Next, select .MCS and Xiliinx, enter the file name to PROM
file next.
Select xcfo2s PROMaddnext, xcfo2 file will open, it asks for one more device to
addOK,in the add device window, select .bit fileopen
Again it asks for do you want to add one more device NOYES
Click any where on the window where you are added the device, Double click on the
generate file in the IMPACT processes window.
We will get the message PROM file Generation is succeeded, if you get the error
message, repeat the steps for PROM file generation
Next Run the Configure device in the processes window, select configure device
using boundary scan and automatically connect to a cable and identify boundary scan
chain option in the IMPACT window Finish
Select the .MCS file in the assign new configuration file windowopen. select .bit
file open,
It asks for do you want to add one more device NO then YES
Right Click on the .mcs Xilinx DeviceProgram, Select Verify and Erase before
programming OK.
Right Click on the .bit DeviceProgram, don’t Select any option OK
In the VLSI trainer Kit, for output, make the respective pin connections using the
connecting wires, other end of the wires connect to the LEDs pins by seeing the pad
report or .ucf file.
for input, make the respective pin connections using the connecting wires, other end
of the wires connect to the, other end of the wire connect to +5V or GND pin for your
Logic ‘1’ or logic ‘0’ inputs.
Give different value to the input ,check the outputs in the LEDs
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AMC Engg College,Dept Of ECE
HDL LAB
LIST OF EXPERIMENTS
Page No
ALU should use combinational logic to calculate an output based on the four
bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-
state the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the example given below.
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AMC Engg College,Dept Of ECE
HDL LAB
Part – B INTERFACING (at least four of the following must be covered using
VHDL/Verilog
1. Control the speed and direction of stepper motor 29
2 Simulate the elevator operations 31
3. Generate different waveforms (sine, square, triangular, ramp etc.) 33
4. Up and down counter using 7 segment display 38
5 Control the speed and direction of DC motor 40
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AMC Engg College,Dept Of ECE
HDL LAB
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AMC Engg College,Dept Of ECE
HDL LAB
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. de-multiplexer, comparator.
a. 2:4 DECODER
module decoder2_4(reset,din,dout);
input reset;
input [1:0] din;
output [3:0] dout;
reg [3:0] dout;
always @(reset,din)
begin
if (reset==1'b1)
begin
dout=4'b0000;
end
else
begin
case(din)
2'b00 : dout=4'b0001;
2'b01 : dout=4'b0010;
2'b10 : dout=4'b0100;
2'b11 : dout=4'b1000;
endcase
end
end
endmodule
module encoder8_3(din,reset,dout);
input [7:0] din;
input reset;
output [2:0] dout;
reg [2:0] dout;
always @(din,reset)
begin
if (reset == 1'b1)
dout = 3'b000;
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AMC Engg College,Dept Of ECE
HDL LAB
else
begin
case (din)
8'b00000001 : dout=3'b000;
8'b00000010 : dout=3'b001;
8'b00000100 : dout=3'b010;
8'b00001000 : dout=3'b011;
8'b00010000 : dout=3'b100;
8'b00100000 : dout=3'b101;
8'b01000000 : dout=3'b110;
8'b10000000 : dout=3'b111;
default : dout=3'b000;
endcase
end
end
endmodule
module prienc123(IR,RA,reset);
input [7:0] IR;
output [2:0] RA;
input reset;
reg [2:0] RA;
always @(IR,reset)
begin
if(reset==1'b1)
RA=3'b000;
else
begin
casex (IR)
8'bxxxxxxx1 : RA= 3'b000;
8'bxxxxxx10 : RA= 3'b001;
8'bxxxxx100 : RA= 3'b010;
8'bxxxx1000 : RA= 3'b011;
8'bxxx10000 : RA= 3'b100;
8'bxx100000 : RA= 3'b101;
8'bx1000000 : RA= 3'b110;
8'b10000000 : RA= 3'b111;
default : RA=3'b000;
endcase
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
b. 8:1 MULTIPLEXER
module mux8_1v(d,reset,sel,y);
input [7:0] d;
input reset;
input [2:0] sel;
output y;
reg y;
always@(reset,sel,d)
begin
if(reset==1)
y = 1'b0;
else
begin
case(sel)
3'd0 : y = d[0];
3'd1 : y = d[1];
3'd2 : y = d[2];
3'd3 : y = d[3];
3'd4 : y = d[4];
3'd5 : y = d[5];
3'd6 : y = d[6];
3'd7 : y = d[7];
endcase
end
end
endmodule
c. BINARY TO GRAY
module bintogray(b,g);
input [3:0] b;
output [3:0] g;
g[3]=b[3];
g[2]=b[3] ^ b[2];
g[1]=b[2] ^ b[1];
g[0]=b[1] ^ b[0];
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
d. GRAY TO BINARY
module gratobin(g,b);
input [3:0] g;
output [3:0] b;
b[3]=g[3];
b[2]=g[3] ^ g[2];
b[1]=g[3] ^ g[2] ^ g[1];
b[0]=g[3] ^ g[2] ^ g[1] ^ g[0];
endmodule
e. 1:8 DEMULTIPLEXER
module demux1_8(reset,y,sel,d);
input y;
input reset;
input [2:0] sel;
output [7:0] d;
reg [7:0] d;
always@(sel,y,reset)
begin
if(reset==1’b1)
d=8’b00000000;
else
begin
case (sel)
3'b000 : d[0] = y ;
3'b001 : d[1] = y ;
3'b010 : d[2] = y ;
3'b011 : d[3] = y ;
3'b100 : d[4] = y ;
3'b101 : d[5] = y ;
3'b110 : d[6] = y ;
3'b111 : d[7] = y ;
default :begin end
endcase
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
f. COMPARATOR
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
3. Write a HDL code to describe the functions of a Full Adder Using three modeling
styles.
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder is
Port (a,b,cin : in std_logic; sum,cout : out std_logic);
end FullAdder;
VERILOG
module FullAdder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
BEHAVIORAL DESCRIPTION
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Seq_Full is
Port ( A,B,Cin : in std_logic;
Sum ,cout: out std_logic);
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AMC Engg College,Dept Of ECE
HDL LAB
end Seq_Full;
VERILOG
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(a,b,cin)
begin
if(a==1'b0 & b==1'b0 & cin==1'b0)
begin
sum=1'b0;
cout=1'b0;
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AMC Engg College,Dept Of ECE
HDL LAB
end
else if(a==1'b0 & b==1'b0 & cin==1'b1)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b0 & b==1'b1 & cin==1'b0)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b0 & b==1'b1 & cin==1'b1)
begin
sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b0 & cin==1'b0)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b1 & b==1'b0 & cin==1'b1)
begin
sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b1 & cin==1'b0)
begin
sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b1 & cin==1'b1)
begin
sum=1'b1;
cout=1'b1;
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
STRUCTURAL DESCRIPTION
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HA is
Port ( I1 : in std_logic;
I2 : in std_logic;
O1 : out std_logic;
O2 : out std_logic);
end HA;
architecture Behavioral of HA is
begin
O1 <= I1 xor I2;
O2 <= I1 and I2;
end Behavioral;
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity orgate is
port ( I1: in std_logic;
I2: in std_logic;
O1: out std_logic);
end orgate;
architecture Behavioral of orgate is
begin
O1 <= I1 or I2;
end Behavioral;
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FA is
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end FA;
architecture Behavioral of FA is
component HA
port (I1, I2 : in std_logic; O1, O2 : out std_logic);
end component;
component orgate
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
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AMC Engg College,Dept Of ECE
HDL LAB
signal s0,c0,c1:std_logic;
begin
HA1 : HA port map (a,b,s0,c0);
HA2 : HA port map (cin,s0,sum,c1);
O1 : orgate port map (c0,c1,cout);
end Behavioral;
VERILOG
module FA(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
HA H1 (a,b,s0,c0);
HA H2 (cin,s0,sum,c1);
or O1 (cout,c0,c1);
endmodule
----------------------------------------------------------------
module HA(a,b,s,c);
input a,b;
output s,c;
xor (s,a,b);
and (c,a,b);
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
module ALU_MIXED(a,b,opcode,enable,y);
input [31:0] a,b;
input [3:0] opcode;
input enable;
output [31:0] y;
reg [31:0] y;
always@(a,b,enable,opcode)
begin
if(enable==1'b1)
begin
case (opcode)
4'b0001 : y = a + b;
4'b0010 : y = a - b;
4'b0011 : y = ~ a;
4'b0100 : y = a * b;
4'b0101 : y = a & b;
4'b0110 : y = a | b;
4'b0111 : y = ~(a & b);
4'b1000 : y = a ^ b;
default: y=32'd0;
endcase
end
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AMC Engg College,Dept Of ECE
HDL LAB
else
begin
y=32'd0;
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
SR FLIP FLOP
module SR_f_f(SR,clk,reset,q,qb);
input [1:0] SR ;
input clk,reset;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
if(reset==1'b1)
q = 1'b0;
else
begin
case (SR)
2'b00 : q = q ;
2'b01 : q = 1'd0 ;
2'b10 : q = 1'd1 ;
2'b11 : q = 1'dZ ;
endcase
end
qb = ~ q;
end
endmodule
D FLIP FLOP
module D_f_f(d,clk,reset,q,qb);
input d;
input clk;
input reset;
output q;
output qb;
reg q,qb;
always@(posedge clk or posedge reset)
begin
if(reset==1'b1)
begin
q<=1'b0;
qb<=1'b1;
end
else
begin
q<=d;
qb<=~d;
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AMC Engg College,Dept Of ECE
HDL LAB
end
end
endmodule
T FLIP FLOP
module T_f_f(clk,reset,t,q,qb);
input clk;
input reset;
input t;
output q;
output qb;
reg q,qb;
always@(posedge clk)
begin
if (reset==1'b1)
begin
q=1'b0;
qb=1'b1;
end
else
begin
if(t==1'b1)
q = ~q;
else
q = q;
end
qb=~q;
end
endmodule
JK FLIP FLOP
module JK_f_f(JK,clk,reset,q,qb);
input [1:0] JK;
input clk;
input reset;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
if (reset==1’b1)
q = 1'd0 ;
else
begin
case(JK)
2'b00 : q = q ;
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AMC Engg College,Dept Of ECE
HDL LAB
2'b01 : q = 1'd0 ;
2'b10 : q = 1'd1 ;
2'b11 : q = ~ q ;
endcase
end
qb = ~q;
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
module SYNC_RESET_BINARY(clk,reset,qout);
input clk;
input reset;
output [3:0] qout;
reg [3:0] qout;
always@(posedge clk)
begin
if(reset==1'b1)
qout=4'b0000;
else
begin
qout=qout+1;
end
end
endmodule
module async_reset_binary(clk,reset,qout);
input clk;
input reset;
output [3:0] qout;
reg [3:0] qout;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
qout=4'b0000;
end
else
begin
qout=qout+1;
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
module sync_reset_bcd(reset,clk,qout);
input reset;
input clk;
output [3:0] qout;
reg [3:0] temp;
assign qout=temp;
always@(posedge clk)
begin
if(reset==1'b1)
temp=4'b0000;
else
begin
temp=temp+1;
if(temp==4'b1001)
temp=4'b0000;
end
end
end
endmodule
module ASYNC_RESET_BCD(clk,reset,qout);
input clk;
input reset;
output [3:0] qout;
reg [3:0] temp;
assign qout=temp;
always@(posedge clk or posedge reset)
begin
if(reset==1'b1)
temp=4'b0000;
else
begin
temp=temp+1'b1;
if(temp==4'b1001)
temp="0000";
end
end
end
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
module tff(q,t,c);
output q;
input t,c;
reg q;
initial
begin
q=1'b1;
end
always @ (posedge c)
begin
if (t==1'b0) begin q=q; end
else begin q=~q; end
end
endmodule
module tff1(q,t,c);
output q;
input t,c;
reg q;
initial
begin
q=1'b0;
end
always @ (posedge c)
begin
if (t==1'b0) begin q=q; end
else begin q=~q; end
end
endmodule
module random(o,clk);
output [3:0]o; input clk;
xor (t0,o[3],o[2]);
assign t1=o[0];
assign t2=o[1];
assign t3=o[2];
tff u1(o[0],t0,clk);
tff1 u2(o[1],t1,clk);
tff1 u3(o[2],t2,clk);
tff1 u4(o[3],t3,clk);
endmodule
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AMC Engg College,Dept Of ECE
HDL LAB
entity motor is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dir : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0);
row : in STD_LOGIC_VECTOR (1 downto 0));
end motor;
end if;
end if;
end process;
dout<= shift_reg;
end Behavioral;
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AMC Engg College,Dept Of ECE
HDL LAB
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity elev is
Port ( kreturn : in STD_LOGIC_VECTOR (03 downto 0);
kscan : inout STD_LOGIC_VECTOR (03 downto 0):="1110";
segmatrix : out STD_LOGIC_VECTOR (03 downto 0);
clock : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (07 downto 0));
end elev;
begin
if(clock'event and clock='1')then
b<=b+1;
if(b=2000000)then
if(temp<a)then temp<=temp+1;
b<=0;
elsif(temp/=a)then
temp<=temp-1;
b<=0;
end if;
end if;
end if;
end process;
process(temp)
type sevseg is array(0 to 15) of std_logic_vector(7 downto 0);
constant segdis: sevseg:=("11111100","01100000","11011010","11110010","01100110",
"10110110","10111110",
"11100000","11111110","11100110","11101110",
"00111110","10011100",
"01111010","10011110","10001110");
begin
seg<=segdis(temp);
segmatrix<="1110";
end process;
end Behavioral;
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AMC Engg College,Dept Of ECE
HDL LAB
3. VHDL code to generate different waveforms (sine, square, triangular, ramp etc.)
using DAC change the frequency and amplitude.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity negramp_wave is
Port ( reset : in std_logic;
clk : in std_logic;
d0 : inout std_logic_vector(11 downto 0));
end negramp_wave;
architecture Behavioral of negramp_wave is
signal clk_div:std_logic_vector(50 downto 0);
signal clkdiv:std_logic;
begin
process(reset,clk)
begin
if reset='1' then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(1);
process(reset,clkdiv)
begin
if(reset='1')then
d0<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
d0<=d0-1;
end if;
end process;
end Behavioral;
SQUARE WAVE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity square_wave is
Port ( reset : in std_logic;
clk : in std_logic;
sq : inout std_logic_vector(11 downto 0));
end square_wave;
architecture Behavioral of square_wave is
signal clk_div:std_logic_vector(50 downto 0);
signal clkdiv:std_logic;
begin
process(reset,clk)
begin
if reset='1' then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(12);
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AMC Engg College,Dept Of ECE
HDL LAB
process(reset,clkdiv)
begin
if(reset='1')then
sq<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
sq<=not sq;
end if;
end process;
end Behavioral;
STAIRCASE WAVE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity staircase_wave is
Port ( reset : in std_logic;
clk : in std_logic;
d0 : inout std_logic_vector(11 downto 0));
end staircase_wave;
architecture Behavioral of staircase_wave is
signal clk_div:std_logic_vector(50 downto 0);
signal clkdiv:std_logic;
begin
process(reset,clk)
begin
if reset='1' then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(1);
process(reset,clkdiv)
begin
if(reset='1')then
d0<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
d0<=d0+333;
end if;
end process;
end Behavioral;
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AMC Engg College,Dept Of ECE
HDL LAB
TRIANGULAR WAVE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular_wave is
Port ( reset : in std_logic;
clk : in std_logic;
d0 : inout std_logic_vector(11 downto 0));
end triangular_wave;
architecture Behavioral of triangular_wave is
signal s1:std_logic_vector(25 downto 1);
signal s2:std_logic;
signal dir:std_logic:='1';
begin
process(reset,clk)
begin
if(reset='1')then
s1<=(others=>'0');
elsif(clk'event and clk='1')then
s1<=s1+1;
end if;
end process;
s2<=s1(1);
process(s2,reset)
begin
if(reset='1')then
d0<=(others=>'0');
elsif(s2'event and s2='1')then
if(dir='1')then
d0<=d0+1;
else
d0<=d0-1;
end if;
end if;
if(d0>"111111111101")then
dir<='0';
elsif(d0<"000000000000")then
dir<='1';
end if;
end process;
end Behavioral;
36
AMC Engg College,Dept Of ECE
HDL LAB
SINE WAVE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sine is
port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sine;
architecture behavioral of sine is
signal c1:std_logic_vector(7 downto 0);
signal i :integer range 0 to 179;
type sine is array (0 to 179) of integer range 0 to 255;
constant value:sine:=
(128,132,136,141,145,150,154,158,163,167,171,175,180,184,188,
192,195,199,203,206,210,213,216,220,223,226,228,231,234,236,
238,241,243,244,246,247,248,249,250,251,252,253,254,255,255,
255,255,254,253,252,251,250,249,248,247,246,244,243,241,238,236,
234,231,228,226,223,220,216,213,210,206,203,199,195,192,188,
184,180,175,171,167,163,158,154,150,145,141,136,132,128,
123,119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,
49,45,42,39,35,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,1,
0,0,0,0,0,0,0,0,1,1,2,3,4,6,7,9,11,12,14,17,19,21,24,27,29,32,
35,39,42,45,49,52,56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,
119,123,128);
begin
process(clk,rst)
begin
if(rst='1') then
c1<=(others=>'0');
elsif(clk'event and clk='1') then
c1<=c1+1;
end if;
end process;
process(c1(3))
begin
if(c1(3)'event and c1(3)='1')then
dac_out<=conv_std_logic_vector(value(i),8);
i<=i+1;
if(i=179) then
i<=0;
end if;
end if;
end process;
37
AMC Engg College,Dept Of ECE
HDL LAB
end behavioral;
4.VHDL code for up and down counter using 7 segment display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seg1 is
Port ( kret : in STD_LOGIC_VECTOR (03 downto 0);
kscan : inout STD_LOGIC_VECTOR (03 downto 0):="0111";
segmatrix : out STD_LOGIC_VECTOR (03 downto 0);
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (07 downto 0));
end seg1;
when "0111"=>
case kret is
when "0111"=> seg<="11111110"; --0
when "1011"=> seg<="01100000"; --1
when "1101"=> seg<="11011010"; --2
when "1110"=> seg<="11110010"; --3
when others=> null;
end case;
when "1011"=>
case kret is
when "0111"=> seg<="01100110"; --4
when "1011"=> seg<="10110110"; --5
when "1101"=> seg<="10111110"; --6
when "1110"=> seg<="11100000"; --7
38
AMC Engg College,Dept Of ECE
HDL LAB
when "1101"=>
case kret is
when "0111"=> seg<="11111110"; --8
when "1011"=> seg<="11100110"; --9
when "1101"=> seg<="11101110"; --a
when "1110"=> seg<="11111101"; --b
when others=> null;
end case;
when "1110"=>
case kret is
when "0111"=> seg<="10011100"; --c
when "1011"=> seg<="01111010"; --d
when "1101"=> seg<="10011110"; --e
when "1110"=> seg<="10001110"; --f
when others=> null;
end case;
39
AMC Engg College,Dept Of ECE
HDL LAB
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dc is
Port ( enable,mtr1,mtr2 : out STD_LOGIC;
clk,rst : in STD_LOGIC;
dir: in std_logic;
row:in std_logic_vector(3 downto 0));
end dc;
architecture Behavioral of dc is
signal div:std_logic_vector(25 downto 0);
signal clkd,tick:std_logic;
signal counter:std_logic_vector(7 downto 0):="11111110";
signal duty_cycle:integer range 0 to 255;
begin
process(clk)
begin
if rising_edge(clk) then
div<=div+1;
end if;
end process;
clkd<=div(8);
enable<='1';
tick<=row(0) and row(1) and row(2) and row(3);
process(clkd)
begin
if rising_edge(clkd) then
counter<=counter+1;
end if;
end process;
process(tick)
40
AMC Engg College,Dept Of ECE
HDL LAB
begin
if falling_edge(tick) then
case row is
when "1110" => duty_cycle<=225;
when "1101" => duty_cycle<=200;
when "1011" => duty_cycle<=175;
when "0111" => duty_cycle<=150;
when others => duty_cycle<=150;
end case;
end if;
end process;
process(rst,dir)
begin
if rst='0' then
mtr1<='0';
mtr2<='0';
else
if dir='0' then
mtr2<='0';
if counter>=duty_cycle then
mtr1<='1';
else
mtr1<='0';
end if;
else
mtr1<='0';
if counter>=duty_cycle then
mtr2<='1';
else
mtr2<='0';
end if;
end if;
end if;
end process;
end Behavioral;
41
AMC Engg College,Dept Of ECE
HDL LAB
VIVA QUATIONS
43
AMC Engg College,Dept Of ECE