DCD QB ET34 Probable questions

UNIT 1
1 Define logic gate, literal, minterm, maxterm, SOP,POS and standard form,PI,EPI
with example

2 Problems on converting one canonical for to another, standard form…

Define canonical form? Translate the following expressions into canonical form:
i) f(a,b,c,d)= a’bc+a’c+bcd ii) F(x,y,z)=(x’+y’)(y+z’)

Give an example for SOP and POS form and convert the given expression into
standard SOP and standard POS form
i) f(a,b,c,d)= a’bc+a’c+bc ii) F(x,y,z)=(x’)(y+z’)

3 Problems on …Simplification of given expression/function using K Map

Define incompletely specified function? Simplify the following function using K-Map.
Y=f(a,b,c,d,)=M(1,2,3,4,9,10)+ X(0,13,14,15)

Get the minimal product expression for N = f(a, b, c, d) = ∏M(0,1,5,6,7,8,9) with

don’t cares: ∏X(10,11,12,13,14,15). Use Karnaugh map for simplification and write
PIs and EPIs.

4 Problems on Simplification of given expression/function using Quine-McCluskey

technique with Petrick’s method…..

H= f(a, b, c, d) = ∑m(0,1,2,4,5,6,8,9,12,13).

f(a,b,c,d)= ∑m(6,7,9,10,13)+ ∑X(1,4,5,11,15).

5 Problems on …Simplification of given expression/function using map entered

variable (MEV) method

let ‘z’ be the map entered variable. V=f(w, x, y, z) =∑m (0, 2, 3, 4, 5, 7, 8, 11, 14,
15).
Let ‘d’ be the map entered variable. V=f (a, b, c, d) =∑m (2, 3, 4, 5, 13, 15) +∑x
(8, 9, 10, 11).

6 Problems on code converters

Design the combinational logic circuit to convert BCD code/Binary code to Excess-
3 code and Viceversa and draw the circuit using minimum number of NAND gates
only/Logic gates.

Design the combinational logic circuit to convert BCD code/Binary code to Gray code
and Viceversa and draw the circuit using minimum number of NAND gates only/Logic
gates.

7 Define the following with examples: i) Priority Encoder ii) Decoder iii) multiplexer
iv)Demultiplexer v) comparators vi) Multiplier vii)adders and subtractors

8 Design and implement and problems on ..

i) Priority Encoder ii) Decoder iii) multiplexer iv)Demultiplexer v) Comparators vi)

Multiplier vii)adders and subtractors

9 Design single digit BCD adder, draw the block diagram and illustrate the operation
with 3-cases.write its important merits.
 UNIT 2
1 Define latch? What is the difference between Latch and Flipflop? Explain how SR
latch acts as a Switch de-bouncer with neat timing diagram.

2 Explain the operation of Master slave JKFF using logic circuit, function table and
timing diagram.

3 What is race-around condition? Explain, how you will avoid this condition with the
help of circuit and timing diagram?

4 Draw the logic network for positive edge/Negative triggered DFF and explain its
operation with timing diagram.

5 State and Derive the characteristic equation for SRFF,JKFF,TFF and DFF.

6 Define Registers. Questions on

i)Unidirectional and universal shift registers ii)Ring and Johnson counters.

7 Derive the excitation table for SRFF,JKFF,TFF and DFF.

8 Design on MOD N Asynchronous up/down counter and MOD N Synchronous

UP/DOWN/random counters using clocked flipflops.

9 Explain Mealy and Moore FSM models with general block diagrams.

Design Mealy sequential network for the following sequence, output is high for non
zero present state when input x =0 using edge triggered JKFF?
0→ 1→2 for x=1, 0→ 2→1 for x=0

Design Moore sequential network for the following sequence, output is high for non zero
present state using edge triggered JKFF. 0→1→2→0 for x=1, 0→2→1→0 for
x=0.

UNIT 3
1 Explain the two basic digital design methodologies of verilog HDL with the help of 4
bit ripple Carry counter.

Explain the design methodology to design a full adder using half adder and write the
verilog module.

Explain the components of a verilog module with neat block view.

2 Define

i) Module
ii) Instance
iii) Pre-defined built-in primitives used in gate level modeling with example
iv) Write the need of HDL language.

3 Describe the lexical conventions and data types used by verilog HDL with examples.

4 Identify the components of verilog module and explain the same with an example of
SR latch.

5 Explain how port provides the interface to verilog module.

6 Identify and explain the logic Gate primitives provided in verilog HDL.

7 Explain how Gate delays allow the weight loss user to specify delays through the
logic circuits.
8 Describe a continuous assignment in data flow modelling in verilog HDL.

9 Explain three ways of specifying delays in continuous assignment.

10 Explain different operator types of verilog HDL.

11 Write a verilog code for 4:1 MUX using

i) data flow statements

ii) conditional operator

12 Write a verilog code for 4 bit full adder using

i) data flow operator

ii) GATE level description

13 Write a verilog code for 4 bit ripple Carry counter using verilog data flow statement
and test it with a stimulus module.

Write the design block and stimulus block for the 3-bit ripple carry counter using TFF
in verilog.

14 Write the module for 2 to 1 line multiplexer using ternary operator. Write the
structural verilog model for 4 to 1 line multiplexer using 2 to 1 line multiplexer.

15 Design 2-bit array multiplier and write the dataflow module with stimulus block.

Design 2-bit array multiplier and write the verilog module using half adder as a
component.

16 Write the verilog module for 1-bit comparator using dataflow modeling.

Draw the logic network for 2-bit comparator using Full adder write the structural
module with stimulus block.

Draw the logic network for 4-bit comparator using Full adder write the structural
module with stimulus block.

17 Write the dataflow verilog module for 4 to 2 priority encoder with highest priority to
LSB bit.

18 Design a 4-bit carry look-ahead adder and write the dataflow verilog module.

19 Write the gate level model with stimulus for the Boolean expression 𝑦 = 𝑎𝑏 + 𝑐′,
where AND, OR & NOT gates takes a delay of 5, 4 & 2 simulation time screen units
respectively & plot the simulation result.

20 Write the dataflow verilog module for 8 to 1 line multiplexer using conditional ternary
operator. Sketch the simulation output for the input 10101101 with all control inputs.

21 Write the Gate level modelling for 2×2 array bit multiplier with stimulus block.

22 Write the gate-level modelling of 3-bit comparator using full adder as a component

UNIT 4
1 Explain the significance of structured procedures in behavioral modelling

2 Define blocking and non blocking procedural assignments.

Illustrate Blocking and Non Blocking assignments with suitable example. State the
application of Non-blocking statement with example.
3 Explain the delay based, event based and level sensitive timing control mechanism
in behavioral modelling

4 Explain conditional statements in verilog HDL

5 Describe multiway branching, looping statements ,sequential and parallel blocks in

behavioral modelling

6 Describe how generate statements allow very low code to be generated dynamically
before simulation begins

7 Describe the difference between

i)tasks and functions

ii) initial & always blocks.

8 Identify and explain the conditions required for task to be defined. Explain task
declaration and invocation

9 Identify and explain the conditions required for function to be defined. Explain
function declaration and invocation

10 Describe briefly automatic functions constant function signed function with an

example

Write the behavioral model for JKFF and plot the simulated waveform.
Write the verilog module to find the factorial of a given number using recursive
function.

Write the behavioral module for 4 to 2 line priority encoder (highest priority to LSB
bit). Write the encoded output for the inputs 1100, 0011, 1010 & 1000.

Write the verilog module with stimulus for the 3-bit counter. Sketch the simulation
result.

Write the verilog module with stimulus for the 3-bit counter using repeat statement.
Sketch the simulation result.
Write the verilog module for 2 to 4 line decoder with active high enable and sketch
the simulation waveform.
Write the importance of functions? Write the verilog module to generate a parity of
a given n-bit vector input using function.

Write the verilog module to convert a 4-bit binary to integer using loop statement.
Write the verilog module to design 4-bit ripple carry adder using full adder task.
Illustrate regular, intra assignment and zero delay control statements with suitable
example.

Illustrate Blocking and Non Blocking assignments with suitable example.

Write the Behavioral model for 4to2 line priority encoder (MSB bit is Highest
priority) with simulation waveform.
Define function. Write the module to find the factorial of given integer number using
recursive functions.

Write the verilog module for SRFF and draw the simulated waveform.
Write the verilog module to generate a clock with a frequency of 1mHz using forever
loop statement.
 Compare tasks and functions. Write the verilog module that shifts a 8- bit value to
the left or right by one bit, based on control bit using function.

Write the behavioral model for 8×1 MUX using case statement and plot the simulated
waveform.
Write the verilog module to find factorial of a given number using while loop.
Differentiate Functions and Tasks and write verilog module to calculate the parity of
a 8-bit binary number using function.

Write the verilog module for 8 to 3 line priority encoder (MSB bit is having the highest
priority) and sketch the output waveform.
Illustrate Blocking and Non Blocking assignments with suitable example. State the
application of Non-blocking statement with example.
Define Task. Write the verilog module to convert integer to binary with parity flag
using task.

Write the behavioral model for 1×8 De-MUX using case statement and plot the
simulated waveform.
Write the verilog module to find factorial of a given number using for loop.
Differentiate Functions and Tasks and write verilog module to calculate the parity of
a 16-bit binary number using function.

Write the verilog module for 8 to 3 line priority encoder (LSB bit is having the highest
priority) and sketch the output waveform.
Illustrate Blocking and Non Blocking assignments with suitable example. State the
application of Non-blocking statement with example.
Define Task. Write the verilog module to convert integer to binary with zero flag
using task.
UNIT 5
1 Define logic synthesis. Explain synthesis design flow from RTL to gates using
flowchart.
2 Why design partitioning is required? Explain horizontal and vertical partitioning.
3 Write the behavioral model to calculate the function y=2x+3, where x is 0 to 4 and
derive the RTL schematic.

Describe the operation of EEPROM and DRAM memories.

Differentiate FPGA and CPLDs? Explain the architecture of FPGA logic block.
Realize the following Boolean expressions using 4×5×3 PLA Device(write PLA
table). F1(a,b,c,d)= ∑m (2,3,5,7,8,9,10,11,13,15), F2(a,b,c,d)= ∑m
(2,3,5,6,7,10,11,14,15) F3(a,b,c,d)= ∑m (6,7,8,9,13,14,15).

Define simulation and synthesis. Illustrate how designer’s mind was used as the logic
synthesis tool.
Write the RTL description for 3-bit magnitude comparator with stimulus to verify the
RTL code.
Illustrate the modeling tips to verilog coding style for better logic synthesis with
examples.

Compare the PROM, PLA and PAL PLDs with their general structures.
Realize the combinational circuit for f1(a,b,c) = ∑(0,1,3,4) and f2(a,b,c)=
∑(1,2,3,4,5) using 3X4X2 PLA.
Describe the operation of CPLD and FPGA architecture with neat block-view.

Define logic simulation and synthesis. Illustrate basic computer aided logic synthesis
process with flowchart.
Using a PROM of an appropriate size, draw the logic diagram in PLD notation for a
PROM realization to convert 3-bit Gray code to binary code.
Write the behavioral model to calculate the function y=2x+3, where x is 0 to 3 and
derive the RTL schematic.
List the different types of PLDs with their general structure and briefly explain these
PLDs.
Describe the mapping of case statement with and without storage to RTL schematic
by taking suitable examples.
Implement the following functions using standard 4×8×3 PAL device. f1(a,b,c)=
∑m(1,2,4,6,7) f2(a,b,c)= ∑m(2,4,5,6) f3(a,b,c)= ∑m(1,4,6).

Define logic synthesis. Describe basic computer aided logic synthesis process with
neat flowchart.
Write the behavioral model to calculate the arithmetical expression Y=2X+5 using
function, where x is 0 to 3 and derive the RTL schematic.
Why design partitioning is required? Explain horizontal and vertical partitioning.

Draw the CLB block for sparten-III FPGA architecture and explain how the circuit
logic can be constructed using this architecture.
Write a note on EPROM and SRAM memories.
Realize the following Boolean expressions using 4×5×3 PLA Device(write PLA
table). F1(a,b,c,d)= ∏(2,3,5,7,8,9,10,11,13,15), F2(a,b,c,d)=
∏(2,3,5,6,7,10,11,14,15) & F3(a,b,c,d)= ∏(6,7,8,9,13,14,15).

Define logic synthesis. Describe basic computer aided logic synthesis process with
neat flowchart.
Write the behavioral model to calculate the arithmetical expression Y=2X+5 using
function, where x is 0 to 5 and derive the RTL schematic.
Why design partitioning is required? Explain horizontal and vertical partitioning.

Draw the CLB block for sparten-II FPGA architecture and explain how the circuit logic
can be constructed using this architecture.
Write a note on E2PROM and SRAM memories.
Realize the following Boolean expressions using 4×5×3 PLA Device(write PLA
table). F1(a,b,c,d)= ∏M(2,3,5,7,8,9,10,11,13,15),
F2(a,b,c,d)= ∏M(2,3,5,6,7,10,11,14,15) & F3(a,b,c,d)= ∏M(6,7,8,9,13,14,15).

define logic synthesis explain the benefits of logic synthesis

identify verilog HDL constructs and operators accepted in logic synthesis.

Understand how the logic synthesis tool interprets these constructs.

explain a typical design flow ,using logic synthesis. describe the components in the
logic synthesis based designed flow.

describe verification of GATE level netlist produced by logic synthesis

explain the techniques for writing efficient RTL descriptions

Describe the portioning techniques to help logic synthesis provide the optimal Gate
level Netlist.

design combinational and sequential circuits, using logic synthesis.

Programs

Write the behavioral Verilog module to implement 3-bit counter

Write the verilog module to implement JKFF using case statement.

Write the verilog module to implement TFF using if else statement.

Write the structural verilog module to implement full adder using half adder.
Write the verilog module to implement SRFF

Write the verilog module to implement DFF.

Write the behavioral Verilog module to implement BCD counter.

Write the verilog module to implement 4 to 2 line priority encoder using casex
statement.

Write the verilog module to implement 2-bit array multiplier using dataflow
modelling

Design and Write the verilog module to implement 2-bit comparator using dataflow
modeling.

Write the verilog module to implement 2 to 4 line decoder using case statement

Write the structural verilog module to implement 4 to 1 line Mux using 2 to 1 line
Mux.

Write the gate level verilog module to implement full subtractor.

Write the gate level verilog module to implement 4-bit binary to gray code
conversion.

Write the behavioral verilog model to implement 4-bit Comparator

Write the gate level verilog module to implement 4-bit parity generator/checker.

Write the dataflow verilog module for full adder and write the test bench (stimulus)
to verify the design.

Write the dataflow verilog module for 1-bit comparator and write the test bench
(stimulus) to verify the design.