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Mini-Project
OBJECTIVES:
MATERIALS:
SPECIFICATIONS:
a. Wire the given circuit below. Note the following pin conventions/connections of the pins
under the header ACEDUINO328BOARD.
Pin # in the Schematic (Header Connection to ACEduino328 Purpose
ACEDUINO328BO Board
1 Port 1 7-segment datum
2 Port 2 7-segment datum
3 Port 3 7-segment datum
4 Port 4 7-segment datum
5 Port 5 7-segment datum
6 Port 6 7-segment datum
7 Port 7 7-segment datum
8 Port 8 7-segment datum
9 Port 9 Latch 1 enable
10 Port 10 Latch 2 enable
2. Develop a 4-digit timer from 00 99 and repeats the count once 99 is reached. Time interval between
number display should be variable.
a. The 74LS373N is an octal transparent latch. The output data (1Q 8Q) are latched when
the ENC is HIGH and when the OC is LOW. (Download a datasheet of this for further
details)
b. The number to be displayed always appears in Ports 1 8. To determine where these data
will be shown, the correct 74LS373 should be enabled. This is done by making the
corresponding Port HIGH. The table above shows which port will enable which latch.
c. By displaying 00 to the two 7-segment display, the following steps must be done.
i. Write to each Port (Port 1 8) the necessary logic level (HIGH or LOW) that will
correctly correspond to a digit.
ii. Enable the Latches one at a time, i.e. Ports 9 10 should have the following
values:
7-segment 1 7-segment 2
Port 9 1 0
Port 10 0 1