Dr. N.G.P.

INSTITUTE OF TECHNOLOGY
(An Autonomous Institution)
(Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai)
Recognized by UGC & Accredited by NAAC with A+ and
NBA (BME, CSE, ECE, EEE and Mechanical)

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

22UIT202-DIGITAL PRINCIPLES AND SYSTEM DESIGNS

LABORATORY MANUAL
(2022-2023 EVEN SEMESTER)

Prepared by:
Dr.S.Nithya Devi, AP (Sl.Gr)/ECE
Dr.P.Divya, AP/ECE
Ms.S.Preethi, AP/ECE

HoD / ECE PRINCIPAL

1
2
 22UIT202-DIGITAL PRINCIPLES AND SYSTEM DESIGNS

PRACTICAL EXCERCISES

LIST OF EXPERIMENTS

1. Implementation of Boolean equations.

2. Implementation of arithmetic circuits.
3. Implementation of Multiplexer & De-multiplexer circuits.
4. Implementation of Encoder and Decoder circuits.
5. Implementation of Latches and Flip-Flops.
6. Basic Logic circuits using VHDL.

TOTAL: 30 PERIODS

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4
 CONTENTS

Exp. No. Name of the Experiment Page No.

1 Study of basic Logic Gates 9

2 Implementation of Boolean equations 17

3 Implementation of arithmetic circuits 21

4 Implementation of Multiplexer & De-multiplexer circuits 27

5 Implementation of Encoder and Decoder circuits 33

6 Implementation of Latches and Flip-Flops 39

7 Basic Logic circuits using VHDL 43

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6
7
 Useful IC Pin details

IC Number Description of IC

7400 Quad 2 input NAND Gate

7402 Quad 2 input NOR Gate

7404 Hex Inverter

7408 Quad 2 input AND Gate

7410 Triple 3-input NAND Gate

7411 Triple 3-Input AND Gate

7421 Dual 4 input AND Gate

7430 8-input NAND Gate

7432 Quad 2-Input OR Gate

7486 Quad EXCLUSIVE-OR Gate

74107 Dual J-K Flip Flop

74174 Hex D Flip Flop

74173 Quad D Flip Flop

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 Ex. No:1
STUDY OF LOGIC GATES
Date:

AIM:
To study about the basic digital IC and verify their truth tables.

COMPONENTS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NAND Gate IC 7400 1
4 NOR Gate IC 7402 1
5 XOR Gate IC 7486 1
6 NOT Gate IC 7404 1
7 IC Trainer Kit 1
8 Patch Cords - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more
input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic
gates form these gates.

AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.

NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.

NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.Op-amps have 5 basic terminals, two input terminals, one output terminal
and two power supply terminals.
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PIN DETAILS OF DIGITAL LOGIC GATES:

10
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

SYMBOL: PIN DIAGRAM:

NOT GATE:

SYMBOL: PIN DIAGRAM:

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X-OR GATE :
SYMBOL : PIN DIAGRAM

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

SYMBOL: PIN DIAGRAM:

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NOR GATE:

SYMBOL: PIN DIAGRAM:

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14
PROCEDURE:
i. Connections are given as per circuit diagram.
ii. Logical inputs are given as per circuit diagram.
iii. Observe the output and verify the truth table.

RESULT:
Thus the truth table of Digital logic gates and the working of various gates are studied and verified.

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16
 Ex. No: 2
IMPLEMENTATION OF BOOLEAN EQUATIONS
Date:

AIM:
To implement the Boolean equations using basic logic gates.

COMPONENTS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1 Digital IC Trainer kit - 1
7400 2
7408 2
2 IC
7432 1
7486 2
3 Connecting wires - As required
4 Breadboard - 1

IMPLEMENTATION FOR 2 INPUT VARIABLES

F = (A + B) . (A + B)

In the given function, it has a complement term, B. So, to represent the compliment input, we are using the
NOT gates at the input side. And to represent the sum term, we use OR gates. See the below logic diagram
for representation of the Boolean function.

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TRUTHTABLE VERIFICATION

A B A+B A + B’ F = (A + B)*( A + B’)

0 0 0 1 0
0 1 1 0 0
1 0 0 1 0
1 1 1 1 1

IMPLEMENTATION FOR 3 INPUT VARIABLES

F = (A + B + C) . (A + B +C) . (A + B + C)

In the given Boolean Function, it has two compliment terms, A and B. So, to represent the compliment
input, we are using the NOT gates at the input side. And to represent the sum term, we use OR gates. See
the below given logic diagram for representation of the Boolean function.

TRUTHTABLE VERIFICATION

A B C A+B+C A’ + B’+C A + B’ + C F = (A + B + C)*( A’ + B’+C)*

(A + B’ + C)
0 0 0 0 1 1 0
0 0 1 1 1 1 1
0 1 0 1 1 0 0
0 1 1 1 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 1 1
1 1 0 1 0 1 0
1 1 1 1 1 1 1

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PROCEDURE:
i. Connections are given as per circuit diagram.
ii. Logical inputs are given as per circuit diagram.
iii. Observe the output and verify the truth table.

RESULT:
Thus the given Boolean equations are implemented using basic gates and its output is verified with its
truth table.

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20
Ex. No: 3

Date:
IMPLEMENTATION OF ARITHMETIC CIRCUITS

AIM:
To design and implement a Half adder, Full Adder, Half Subtractor and Full Subtractor using basic
gates.
COMPONENTS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1 Digital IC Trainer kit - 1
7400 2
7408 2
2 IC
7432 1
7486 2
3 Connecting wires - As required
4 Breadboard - 1
THEORY:

Half Adder

The half adder takes two single bit binary number sand produces a sum and a carry–out,
called “carry”. Written as a standard sum, the last row represents the following: 01+01=10. The sum
column indicates the number to be written in the unit’s column, immediately below the two 1’s. We
write a 0 and carry a 1. There is no possibility of a carry–in for the unit’s column, so we do not
design for such. Another way is to say that there is a carry–in; it isalways0.

Half Subtractor

Subtracting a single-bit binary value B from another A (i.e. A -B) produces a difference
bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize
it is called a half subtractor.

Full Adder

The full adder in decimal arithmetic would be used for the other columns: the
ten’scolumn, the hundred’s column, and so on. For these columns, a non–zero carry–in is a
distinctpossibility Considered this way, we might write our sums table as follows. 2 + 2 = 4, if
thecarry–inis 0,and2+2=5,whenthe carry–inis1.

Full Subtractor

Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction.

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 HALFADDER:

TRUTH TABLE: LOGICAL DIAGRAM:

LOGICAL EXPRESSION:

HALF SUBTRACTOR

Logic Symbol of Half Subtractor Truth Table of Half Subtractor

LOGICAL EXPRESSION:

Difference = A ⊕ B
Borrow = A' B

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 Circuit Diagram of Half Subtractor

FULL ADDER:

TRUTH TABLE: LOGICAL DIAGRAM:

LOGICAL EXPRESSION:

S = Axor B xorCin

Cout = AB + BCin + Cin A or Cout = AB + Cin (A xor B)

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FULL SUBTRACTOR:

Logic Symbol of Full subtractor

Truth Table of Full subtractor

LOGICAL EXPRESSION:

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin

Circuit Diagram of Full subtractor

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PROCEDURE:
i. Connections are given as per circuit diagram.
ii. Logical inputs are given as per circuit diagram.
iii. Observe the output and verify the truth table.

RESULT:
Thus the Half Adder and Half Subtractor using basic gates was designed, implemented and verified
with its truth table.

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 Ex.No: 4
IMPLEMENTATION OF MULTIPLEXER AND DE -
Date: MULTIPLEXER CIRCUITS

AIM:

To design and implement multiplexers and de-multiplexers using logic gates.

COMPONENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QUANTITY

1. 3I/P AND GATE IC7411 4
2. OR GATE IC7432 3
3. NOT GATE IC7404 2
4. IC TRAINER KIT - 1
5. PATCH CORDS -

THEORY:

Multiplexer:
Multiplexer means transmitting a large number of information units over a smaller number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection
of a particular input line is controlled by a set of selection lines. Normally there are 2 n input
line and n selection lines whose bit combination determine which input is selected.

De-Multiplexer:

The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the
exact opposite of the Multiplexer. The demultiplexer takes one single input data line and then
switches it to anyone of a number of individual output lines one at a time. The demultiplexer
converts a serial data signal at the input to a parallel data at its output lines.

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4:1MULTIPLEXER
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 Y=OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Y=D0 S1’S0’+D1S1’S0+D2S1 S0’ + D3S1S0

LOGIC DIAGRAM FOR MULTIPLEXER:

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1:4 DEMULTIPLEXER:
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

TRUTH TABLE:

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

Y3=S1S0I
Y2=S1S0′I
Y1=S1′S0I
Y0=S1′S0′I

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LOGIC DIAGRAM:

3- INPUT AND GATE(IC 7411) PIN DIAGRAM:

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 PROCEDURE:

i. Connections are given as per circuit diagram.

ii. Logical inputs are given as per circuit diagram.
iii. Observe the output and verify the truth table.

RESULT:
Thus 4:1 multiplexer and 1:4 demultiplexer using logic gates was designed, implemented and verified
with truthtable.

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32
 Ex.No: 5
IMPLEMENTATION OF ENCODER AND
Date: DECODER CIRCUITS

AIM:
To design and implement encoder and decoder using logic gates.

COMPONENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QUANTITY

1. 3I/P AND GATE IC7411 2
2. ORGATE IC7432 3
3. NOTGATE IC7404 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - As required

THEORY:

ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n input
lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value.
In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the
corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into coded
output where input and output codes are different. The input code generally has fewer bits than the output
code. Each input code word produces a different output code word i.e there is one to one mapping can be
expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input
producing 2n possible outputs. 2n output values are from 0 through output 2n-1

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8:3 ENCODER:

TRUTH TABLE
INPUT OUTPUT
Yo Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

From Truth table, we can write the Boolean functions for each output as
A=Y7+Y6+Y5+Y4
B=Y7+Y6+Y3+Y2
C=Y7+Y5+Y3+Y1

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LOGIC DIAGRAM:

3:8 DECODER:
TRUTH TABLE

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From Truth table, we can write the Boolean functions for each output as

LOGIC DIAGRAM:

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 PROCEDURE:

i. Connections are given as per circuit diagram.

ii. Logical inputs are given as per circuit diagram.
iii. Observe the output and verify the truth table.

RESULT:
Thus 8:3 encoder and 3:8 decoder using logic gates was designed, implemented and verified with
truth table.

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38
 Ex. No: 6
IMPLEMENTATION OF LATCHES AND FLIP-FLOPS
Date:

AIM:-

To design and implement the different types of latches and flip-Flops by verifying its Truth table
(i) RS-Type
(ii) D- Type
(iii) T- Type

COMPONENTS REQUIRED: -

Sl.No. COMPONENT SPECIFICATION QUANTITY

1. 3 I/P NAND GATE IC7410 1
2. 2 I/P NAND GATE IC7400 1
3. NOTGATE IC7404 1
4. ICTRAINERKIT - 1
5. PATCHCORDS - As required

THEORY:

Flip-Flop :

Flip-flop is a basic digital memory circuit, which stores one bit of information. Flip flops are the
fundamental blocks of most sequential circuits. It is also known as a bistable multivibrator or a binary or
one-bit memory. Flip-flops are used as memory elements in sequential circuit. The output is obtained in a
sequential circuit from combinational circuit or flip-flop or both. The state of flip-flop changes at active
state of clock pulses and remains unaffected when the clock pulse is not active. In part icular, clocked flip
flops serve as memory elements in synchronous sequential Circuits and unclocked flip -flops (i.e., latches)
serve as memory elements in asynchronous sequential circuits.

Latch :
Latch is an electronic device, which changes its output immediately based on the applied input. It
is used to store either 1 or 0 at any specified time. It consists of two input s namely “SET” and RESET and
two outputs, which are complement to each.

SR-Flip Flop:

The SET-RESET flip-flop consists of two NOR gates and also two NAND gates. These flip-flops are
also called S-R Latch. The design of these flip flops also includes two inputs, called the SET [S] and RESET
[R]. There are also two outputs, Q and Q'.

D-Flip Flop:

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 D flip – flops are also called as “Delay flip – flop” or “Data flip – flop”. They are used to store 1 – bit
binary data. They are one of the widely used flip – flops in digital electronics. Apart from being the basic
memory element in digital systems, D flip – flops are also considered as Delay line elements and Zero –
Order Hold elements. D flip – flop has two inputs , a clock (CLK) input and a data (D) input and two outputs;
one is main output represented by Q and the other is complement of Q represented by Q’.

T-Flip Flop:

The "T Flip Flop" is designed by passing the AND gate's output as input to the NOR gate of the "SR
Flip Flop". The inputs of the "AND" gates, the present output state Q, and its complement Q' are sent back to
each AND gate. The toggle input is passed to the AND gates as input.

Circuit Diagram & Truth table:

SR FLIPFLOP

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D Flip-Flop
TRUTHTABLE

T Flip-flop TRUTHTABLE

Procedure: -

1. Connections are made as per circuit diagram.

2. Verify the truth table for various combinations of inputs.

RESULT:
Thus the various types of latches and flip-flops are implemented and its truthtable are verified
successfully.

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42
 Ex. No: 7
Basic Logic circuits using VHDL
Date:

AIM:

To simulate the output waveform for basic logic gates using VHDL programming.

APPARATUS REQUIRED:

i. Personal Computer
ii. Xilinx ISE Simulator / ModelSim

PROGRAMS:

VHDL Code for OR Gate:

Library IEEE;
use IEEE.std_logic_1164.all;
entity OR_gate is
port(A : in std_logic;
B : in std_logic;
Y : out std_logic);
end OR_gate;
architecture orLogic of OR_gate is
begin
Y <= A OR B;
end orLogic;

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VHDL Code for AND Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity andd_Gaate is
port(A: in std_logic;
B: in std_logic;
Y: out std_logic);
end andd_Gaate;
architecture andLogic of andd_Gaate is
begin
Y <= A AND B;
end andLogic;

VHDL Code for NOT Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity not_gate is
port(A : in std_logic;
Y : out std_logic);
end not_gate;
architecture notLogic of not_gate is
begin
Y <= not(A) ;
end notLogic;

VHDL Code for NOR Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port(A: in std_logic;
B: in std_logic;
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 Y: out std_logic);
end nor_gate;
architecture norLogic of nor_gate is
begin
Y <= not(A OR B);
end norLogic;

VHDL Code for NAND Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity nand_gate is
port(A: in std_logic;
B: in std_logic;
Y: out std_logic);
end nand_gate;
architecture nandLogic of nand_gate is
begin
Y <= not (A and B);
end nandLogic;

VHDL Code for XOR Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity xor_gate is
port(A: in std_logic;
B: in std_logic;
Y: out std_logic);
end xor_gate;
architecture xorLogic of xor_gate is
begin
Y <= A xor B; 45
end xorLogic;

VHDL Code for XNOR Gate:

library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port(A : in std_logic;
B : in std_logic;
Y : out std_logic);
end xnor_gate;
architecture xnorLogic of xnor_gate i
begin
Y <= not(A xor B);
end xnorLogic;

PROCEDURE:

i. Creating a New Project in ISE

A project is a collection of all files necessary to create and to download a design to a selected FPGA
or CPLD device.
To create a new project for this tutorial:
1. Select File > New Project. The New Project Wizard appears.
2. First, enter a location (directory path) for the new project.
3. Type tutorial in the Project Name field. When you type tutorial in the Project Name field, a
tutorial subdirectory is created automatically in the directory path you selected.
4. Select HDL from the Top‐Level Module Type list, indicating that the top‐level file in your
project will be HDL, rather than Schematic or EDIF.
5. Click Next to move to the project properties page.
6. Fill in the properties in the table as shown below Device
Family: CoolRunner XPLA3 CPLDs Device: xcr3128xl
Package: TQ144
Speed Grade: -7
Top‐Level Module Type: HDL Synthesis Tool: XST
(VHDL/Verilog) Simulator: ModelSim
Generated Simulation Language: VHDL or Verilog, depending on the language you want to use
when running behavioral simulation.

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When the table is complete, your project properties should look like the following:

Click Next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be created.

ii. Creating an HDL Source

Determine the language that you wish to use for the tutorial. Then, continue either to the
“Creating a VHDL Source” section below.

This simple AND Gate design has two inputs: A and B. This design has one output called C
Click New Source in the New Project Wizard to add one new source to your project.
Select VHDL Module as the source type in the New Source dialog box.
Type in the file name andgate.
Verify that the Add to project checkbox is selected.
Click Next.

iii. Define the ports for your VHDL source.

In the Port Name column, type the port names on three separate rows: A, B and C.
In the Direction column, indicate whether each port is an input, output, or inout. For A and B,
select in from the list. For C, select out from the list.
47
1. Click Next in the Define VHDL Source dialog box.
2. Click Finish in the New Source Information dialog box to complete the new source file template.
3. Click Next in the New Project Wizard.
4. Click Next again.
5. Click Finish in the New Project Information dialog box.
ISE creates and displays the new project in the Sources in Project window and adds the andgate.vhd file to
the project.
6. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL
file in the ISE Text Editor. The andgate.vhd file contains:
o Header information.
o Library declaration and use statements.
o Entity declaration for the counter and an empty architecture statement.
7. In the header section, fill in the following fields:
Design Name: andgate.vhd Project Name:
andgate
Target Device: xcr3128xl- TQ144
Description: This is the top level HDL file for an up/down counter.
Dependencies: None
Note: It is good design practice to fill in the header section in all source files.
8. Below the end process statement, enter the following line:
C <= A and B;
9. Save the file by selecting File > Save.

iv. Checking the Syntax of the New Counter Module

When the source files are complete, the next step is to check the syntax of the design. Syntax errors and
typos can be found using this step.
1. Select the counter design source in the ISE Sources window to display the related processes in the
Processes for Source window.
2. Click the “+” next to the Synthesize-XST process to expand the hierarchy.

48
3. Double-click the Check Syntax process.

When an ISE process completes, you will see a status indicator next to the process name.
If the process completed successfully, a green check mark appears.
If there were errors and the process failed, a red X appears.
A yellow exclamation point means that the process completed successfully, but some warnings occurred.
An orange question mark means the process is out of date and should be run again.
4. Look in the Console tab of the Transcript window and read the output and status messages produced by
any process that you run.

v. Simulation

1. Double click Launch ModelSim Simulator in the Process View window.

10. Right Click ‘a’ to open a context menu.

11. Select Force or Clock to add the signal.

49
12. Define the Clock or Force signal to load appropriate signal

13. Run the simulation by clicking the Run icon in the Main or Wave window toolbar.

50
14. Waveform can be observed in the wave window

51
OUTPUT: OR Gate:

OUTPUT: AND Gate:

52
OUTPUT: NOT Gate:

OUTPUT: NOR Gate:

53
OUTPUT: NAND Gate:

OUTPUT: XOR Gate:

54
OUTPUT: XNOR Gate:

RESULT:
Thus the VHDL programming is written for basic logic gates like AND, OR, NOT, NOR, NAND,
XNOR and XOR and the waveforms are simulated & verified using ModelSim.

55