LAB EXPERIMENTS

Title: DIGITAL SYSTEMS DESIGN

Name:
Sinchan Shetty 22BCE5238
Siddhant Bhardwaj 22BCE5247
Madhurima Nayak 22BPS1226
Vraj Amin 22BPS1227

Course code: BECE102P

LAB Slot: L51+L52
Faculty Name: Prof. Telagam Setti Sunilkumar

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 INDEX

Sr. Experiment Name Page no

No.
1. Construction of basic logic 3
gates+Software
2. Design and implementation of 15
Boolean expression.
3. Design and construction of Half 19
and Full adder + Software .
4. Design and Construction of Half 27
and Full- Subtractor.
5. Implementation of Multiplexer 30
and de-Multiplexer+Software.
6. Implementation of Decoder and 42
Encoder + Software.
7. Implementation of Carry Look 48
Ahead Adder (2-bit)

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 EXPERIMENT-1
AIM:
Construct and verify the basic logic gates (NOT, AND, OR,
NAND, NOR, XOR) using its truth table.

S. No. COMPONENT SPECIFICATION QUANTITY

1. 2-INPUT AND GATE IC 7408 1
2. 1-INPUT NOT GATE IC 7404 1

3. 2-INPUT NAND GATE IC 7400 1

4. 2-INPUT NOR GATE IC 7402 1
5. 2-INPUT XOR GATE IC 7486 1
6. 2-INPUT OR GATE IC 7432 1

7. DIGITAL TRAINER KIT - 1

8. Connecting wires - few

THEORY/OBSERVATION :

• AND GATE: gives a high output (1) only if all its inputs are high. The output is low level when any
one of the inputs is low.

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• NOT GATE: A circuit that produces an inverted version of the input at its output. The output is
high when the input is low. The output is low when the input is high.
• Also knaown as In

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 • NAND GATE: The outputs of all NAND gates are high if any of the inputs are low. The output is
low level when both inputs are high.

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 • NOR GATE: The outputs of all NOR gates are low if any of the inputs are high. The output is high
when all inputs are low.

• XOR GATE: A circuit which will give the output is high only when odd number of is high.

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EXPERIMENT-1 (Software)
AIM:
To design and simulate the combinational logic Gates using EDA Playground
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 TOOLS:
Software: ModelSim

VERILOG CODING & RESULTS:

• AND GATE
BEHAVIORAL LEVEL MODELING:

GATE-LEVEL MODELING:

DATA FLOW MODELING:

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 OUTPUT:

• XOR GATE
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BEHAVIORAL LEVEL MODELING:

GATE-LEVEL MODELING:

DATA FLOW MODELING:

OUTPUT:
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• NAND GATE
BEHAVIORAL LEVEL MODELING:

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 GATE-LEVEL MODELING:

DATA FLOW MODELING:

OUTPUT:

• NOR GATE
BEHAVIORAL LEVEL MODELING:
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GATE-LEVEL MODELING:

DATA FLOW MODELING:

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OUTPUT:

INFERENCE:
Thus combinational logic gates (AND,XOR,NAND,NOR) are
constructed using three types of Verilog modeling and its
logical functions is verified by simulation.
The outputs have been verifies and objectives and behaviour
of these logic gates have been understood by the student.

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EXPERIMENT-2

Aim: To verify and implement the Boolean Expression

F = ~((A+B) .(C+D)) using hardware as well as software.
a) Implement in trainer kit.
b) Data flow and gate level modelling

TOOLS REQUIRED:
SOFTWARE: ModelSim

HARDWARE:

S. No. COMPONENT SPECIFICATION QUANTITY

1. 2-INPUT NAND GATE IC 7400 1

2. 2-INPUT OR GATE IC 7432 1

3. DIGITAL IC TRAINER KIT - 1

4. Connecting wires - few

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 IC PIN DIAGRAM:

LOGIC DIAGRAM:

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 TRUTH TABLE:

PROCEDURE (Hardware) :
• Use 2 OR gates each for (A,B) and (C,D).
• The output of both the OR gates now acts a s a input for a new
NAND Gate.
• The output of this NAND gate is our final Output(F).

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VERILOG CODE:
GATE LEVEL MODELLING:

DATA LEVEL MODELLING:

OUTPUT:

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RESULT: Thus F = ~((A+B).(C+D)) is verified in hardware by
designing the circuit and in software by using the different
models of code. Thus the student had now understood to
design logical circuits.

EXPERIMENT-3
AIM: Design and construct half adder circuits and full
adder circuits and verify the truth table using logic
gates and EDA Playground software.
a) Implement in trainer kit.
b) Data flow and Gate level modelling

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COMPONENTS REQUIRED:

HARDWARE->

a) Half Adder:
S. No COMPONENT SPECIFICA QUANTITY
TION

1 2-INPUT AND IC 7408 1

GATE
2 2-INPUT XOR IC 7486 1
GATE

3 DIGITAL TRAINER KIT - -

4 Connecting wires - -

b) Full Adder:

S. No COMPONENT SPECIFICA QUANTITY

TION

1 2-INPUT AND IC 7408 2

GATE
2 2-INPUT XOR IC 7486 2

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 GATE

3 2-INPUT OR GATE IC 7432 1

4 DIGITAL TRAINER KIT - -

5 Connecting wires - -

SOFTWARE-> ModelSim.

THEORY:

An adder is a digital logic circuit in electronics that

implements the addition of numbers. A typical
adder circuit produces a sum bit (denoted by S) and
a carry bit (denoted by C) as the output. Adders are
classified into two types: half adder and full adder.

HALF ADDER: 2-INPUT Half adder is a combinational

arithmetic circuit that adds two one-bit numbers
and produces a sum bit (S) and carry bit (C) as the
output. The half adder can add only two input bits
(A and B).

FULL ADDER: A full adder is a digital circuit that adds three

one-bit binary numbers, two operands and a carry bit. The
adder outputs two numbers, a sum and a carry bit. Full
adders are made from XOR, AND, OR gates in hardware.

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TRUTH TABLE:
a) HALF ADDER:

LOGIC DIAGRAM:

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B)FULL ADDER:

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VERILOG CODE:

Half Adder:
Gate Model:
module ha_gl(output sum,carry,input a,b);
xor(sum,a,b);
and(carry,a,b);
endmodule

Behavioral Model:
module ha_b(output reg sum,carry,input a,b);
always@(a or b)
{carry,sum}=a+b;
endmodule

Data Flow Model :

module ha_df(output sum,carry,input a,b);
assign sum=a^b;

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assign carry=a&b;
endmodule
Full Adder:

Gate model:
module fa_gl(output sum,carry,input a,b,c, wire m,n,p);
xor(n,a,b);
xor(sum,n,c);
and(m,n,c);
and(p,a,b);
or(carry,m,p);
endmodule

Data Flow model:

module fa_df(output sum,carry,input a,b,c, wire m,n,p);
assign n=a^b;
assign sum=n^c;
assign m=n&c;
assign p=a&b;
assign carry=m|p;
endmodule

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Behavioral model:
module fa_b(output reg sum,carry,input a,b,c);
always@(a or b or c)
{carry,sum}=a+b+c;
endmodule

OUTPUT:
a) HALF ADDER:

b) FULL ADDER:

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RESULT:
Thus, half adder logic circuits and full adder
logic circuits are constructed using basic
logic gates and their truth tables are verified
in both hardware and software .

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EXPERIMENT-4
AIM: Design and construct half-subtractors circuits
and full subtractors circuits and verify the truth table
using logic gates.Implement in trainer kit.

HARDWARE:

S. No. COMPONENT SPECIFICATION QUANTITY

1. 2-INPUT AND GATE IC 7408 1
2. 2-INPUT OR GATE IC 7432 1
3. 1-INPUT NOT GATE IC 7404 1
4. 2-INPUT XOR GATE IC 7486 1
5. DIGITAL TRAINER KIT - 1
6. Connecting wires - few

A) HALF SUBTRACTOR
TRUTH TABLE:
INPUTS OUTPUTS
A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

LOGIC DIAGRAM:
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 B) FULL SUBTRACTOR
Truth Table:
INPUTS OUTPUTS
A B Bin DIFFERNECE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

LOGIC DIAGRAM:

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 RESULT:

Thus,data path elements such as half subtractor, full subtractor logic

circuits are constructed using basic logic gates and their truth tables are
verified.

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EXPERIMENT-5
Aim: To implement MUX and DEMUX using logic gates
and verify using truth table and EDA Playground.

Components Required:

HARDWARE->
S. No. COMPONENT SPECIFICATION QUANTITY
1. 2-INPUT AND GATE IC 7408 2
2. 2-INPUT OR GATE IC 7432 1
3. 1-INPUT NOT GATE IC 7404 1

MUX:
4:1 Multiplexer: In the 4×1 multiplexer, there is a total of four
inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e., S0 and
S1 and single output, i.e., Y.

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BLOCK DIAGRAM and CIRCUIT DIAGRAM

TRUTH TABLE:

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The logical expression of the term Y is as follows:
Y=S1'.S0'.A0+S1'.S0.A1+S1.S0'.A2+S1.S0 A3

DEMUX:
1:4 Demultiplexer: THEORY: A 1-to-4 demultiplexer has a
single input (D), two selection lines (S1 and S0) and four
outputs (Y0 to Y3).

BLOCK DIAGRAM

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TRUTH TABLE:

The logical expression of the term Y is as follows:

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Y0=S1' S0' A
y1=S1' S0' A
y2=S1' S0' A
y3=S1' S0' A

Logical circuit of the above expressions is given below:

HARDWARE:
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PROCEDURE:
1. Place the IC on IC trainer kit
2. Connect the Vcc and ground to respective pins the of IC
trainer kit
3. Connections are given as per logic diagram
4. Connect the inputs to the input switches provided in the
IC trainer kit
5. Connect the outputs to the switches of output LED’s
6. Apply various combinations of input according to the truth
table
7. Observe the condition of output LED’s and verify the truth
table

VERILOG CODE: MUX

GATE –LEVEL MODELLING:

module m41(out, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
wire s0bar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);

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 and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar),
(T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule

DATA –FLOW MODELLING:

module m41 (
input a,
input b,
input c,
input d,
input s0, s1,
output out
);
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule

TESTBENCH FOR MUX:

module muxt_b;

reg [3:0] a;

reg [1:0] s;
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wire o;

m41 dut (.a(a),.s(s),.o(o));

initial begin

#10 a=4’b1010;

#10 s=2’b00;

#10 s=2’b01;

#10 s=2’b10;

#10 s=2’b11;

#10 $stop;

end

Endmodule

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OUTPUT:

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VERILOG CODE: DEMUX

GATE–LEVEL MODELLING:
module demux_1_to_4(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);
not(s1n,s1),(s0n,s0);
and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1);
endmodule

DATA-FLOW MODELLING :
module demux_1_to_4( input d, input s0, input s1, output
y0, output y1, output y2, output y3 );
assign s1n = ~ s1;
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assign s0n = ~ s0;
assign y0 = d& s0n & s1n;
assign y1 = d & s0 & s1n;
assign y2 = d & s0n & s1;
assign y3 = d & s0 & s1;
endmodule

TESTBENCH FOR DEMUX:

module demux4X1_tb();
reg[3:0]a;
reg[1:0]sel;
wire o0,o1,o2,o3;
demux_1_to_4
dut(.a(a),.sel(sel),.o0(o0),.o1(o1),.o2(o2),.o3(o3));
initial
begin
$dumpfile(“dump.vcd”);
$dumpvars(1);
end
initial
begin

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sel=2’b00;a=4’b0101;
#5
sel2’b01;a=4’b0101;
#5
sel2’b10;a=4’b0101;
#5
sel2’b11;a=4’b0101;
#5
$finish();
end
Endmodule

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OUTPUT:

RESULT: Thus, the multiplexer and demultiplexer logic circuit

is constructed using basic logic gates and its truth table is
verified using trainer kit and also, the simulation was carried
out for MUX and De-MUX using Verilog Software to verify its
functionality.

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EXPERIMENT-6

Aim: To implement Encoder and Decoder using logic

gates and verify using truth table and software.

Components
Required:

HARDWARE
S. No. COMPONENT SPECIFICATION QUANTITY
1. 2-INPUT AND GATE IC 7408 2
2. 2-INPUT OR GATE IC 7432 1
3. 1-INPUT NOT GATE IC 7404 1

Priority Encoder(4X2):-
The priority encoder is a combinational logic circuit that contains
2^n input lines and n output lines and represents the highest
priority input among all the input lines. When multiple input lines
are active high at the same time, then the input that has the
highest priority is considered first to generate the output.

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Block Diagram

Truth Table:

Verilog:

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Test Bench

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 Decoder-
Decoder is a combinational circuit which transforms given
inputs to maximum number of outputs(2^n and n are
giveninputs).

(Here L means 0 and H means

1)The logical expression will
be Y=S1’S0’+S1’S0+S1S0’+S1S0

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Page 48 of 54
 Result-Hence 2x4 decoder and
Priority encoder were designed and
their outputs were verified.

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EXPERIMENT-7
AIM: Implementation of carry look ahead adder
for 3 bit numbers.
HARDWARE REQUIRED :
Ex-OR gates, AND gates, XOR gates

CIRCUIT DIAGRAM:

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Equation of carry being generated:

Gi=carry generator
Pi=carry propagator

Truth Table:

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Procedure:
• Begin by configuring the hardware
components according to the circuit
schematic given. Place the integrated circuits
(ICs) such as AND gates, OR gates, and XOR
gates on the breadboard or PCB. Connect
them to a power source.
• Assuring a consistent 5V DC source for the
circuit.
• Push buttons are used to enter two 3-bit
binary numbers indicating the values you
want to add. This step simulates actual data
entry.
• Logic Design: This is an important stage in the
experiment. Create the logic for the
• Look-ahead adder with three bits of carry.
Refer to the whole adder circuit in the
diagram.
• Define the terms "carry generate" (G_i)

• For each level of the adder, "carry propagate"

(P_i) variables are used.

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CONCLUSION :
In this hardware experiment, we successfully designed and implemented a 3-bit Carry Look-
Ahead Adder using logic gates for binary addition. We observed the operation of the adder
for various inputs and analyzed its performance.

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