Laboratory Manual of

Digital Electronics and Microprocessor

(DEM)

For completion of term work of 3rd

semester curriculum program

Bachelor of Technology

In

COMPUTER ENGINEERING

DEPARTMENT OF COMPUTER ENGINEERING

Dr. BABASAHEB AMBEDKAR TECHNOLOGICAL

UNIVERSITY

Lonere-402 103, Tal. Mangaon, Dist.

Raigad (MS) INDIA

LIST OF EXPERIMENTS

1. Simplification, realization of Boolean expressions using logic gates/universal

gates
2. Realization of half/full adder & half/full subtractors using logic gates.

3. Realization of parallel adder/subtractors using 7483 chip, BCD to Excess-

3code conversion & vice versa.

4. Realization of binary to gray code conversion & vice versa.

5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits & code

converter.

6. Realization of one/two bit comparator and study of 7485 magnitude

comparator.

7. Use of a) Decoder chip to drive LED display & b) Priority encoder.

8. Truth table verification of flip-flops: i) JK Master Slave ii) T type iii) D

type.

9. Realization of 3-bit counters as a sequential circuit & MOD-N counter

design (7476, 7490, 74192, 74193).

10. Writing & testing of sequence generator.

11. Design of FSM: Moore machine, Mealy machine.

 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 1

TITLE : Simplification, realization of Boolean expressions using logic gates/universal

gates.

AIM : To study about logic gates and verify their truth tables.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. AND GATE IC 7408
2. OR GATE IC 7432
3. NOT GATE IC 7404
4. NAND GATE 2 I/P IC 7400
5. NOR GATE IC 7402
6. X-OR GATE IC 7486
7. NAND GATE 3 I/P IC 7410
8. PATCH CORD -

THEORY:
Circuit that takes the logical decision and the process are called
logic gates. Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates.

AND GATE:
The AND gate performs a logical multiplication commonly known
as AND function. The output is high when both the inputs are high.
The output is low level when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as
 OR function. The output is high when any one of the inputs is high.
The output is low level when both the inputs are low.

NOT GATE :
The NOT gate is called an inverter. The output is high when the
input is low. The output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is
high when both inputs are low and any one of the input is low .The
output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high
when both inputs are low. The output is low when one or both inputs are high.

X-OR GATE :
The output is high when any one of the inputs is high. The
output is low when both the inputs are low and both the inputs are high.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

AND GATE :

OR GATE
NOT GATE :

XOR GATE
2-INPUT NAND GATE :

3-INPUT NAND GATE :

NOR GATE :

CONCLUSION :
Thus, we have studied the Simplification, realization of Boolean expressions using
logic gates/universal gates.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 2

TITLE : Realization of half/full adder & half/full subtractors using logic gates.
AIM: To design and construct half adder, full adder, half subtracter and
full subtracter circuits and verify the truth table using logic gates.

HARDWARE REQUIREMENTS :

Sl.No. COMPONENT SPECIFICATION

1. AND GATE IC 7408
2. X-OR GATE IC 7486
3. NOT GATE IC 7404
4. OR GATE IC 7432
3. IC TRAINER KIT -
4. PATCH CORDS -

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and
two outputs one from the sum 'S' and other from the carry ' c' into the
higher adder position. Above circuit is called as a carry signal from
the addition of the less significant bits sum from the X-OR Gate the carry out
from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic
sum of input; it consists of three inputs and two outputs. A full adder is
useful to add three bits at a time but a half adder cannot do so. In full adder sum
output will be taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate.

The half subtractor has two input and two outputs. The outputs are
difference and borrow. The difference can be applied using X-OR
Gate, borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT
Gates. In a full subtractor the logic circuit should have three inputs and
two outputs. The two half subtractor put together gives a full subtractor.
The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output
of the half subtractor and the second term is the inverted difference output of first
X-OR.

LOGIC
DIAGRAM:

HALF ADDER

TRUTH TABLE:

A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 K-Map for SUM : K-Map for CARRY :

LOGIC DIAGRAM:
FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE
K-Map for SUM :

SUM = A'B'C + A'BC' + ABC' + ABC

K-Map for CARRY

CARRY = AB + BC + AC
LOGIC DIAGRAM :

HALF SUBTRACTOR

TRUTH TABLE

K-Map for DIFFERENCE

DIFFERENCE = A'B +
AB'
K-Map for BORROW

BORROW = A'B

LOGIC DIAGRAM :

FULL
SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR :

TRUTH TABLE:

K-Map for DIFFERENCE

Difference = A'B'C + A'BC' + AB'C' + ABC

 Borrow = A'B + BC + A'C

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

CONCLUSION :
Thus, we have studied the Realization of half/full adder & half/full subtractors
using logic gates.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 3

TITLE : Realization of parallel adder/subtractors using 7483 chip, BCD to Excess-

3 code conversion & vice versa.
AIM : To realize IC 7483 as parallel adder / subtractor and conversion of BCD to
Excess-3 code and vice versa.

HARDWARE REQUIREMENTS :

Sl.No. COMPONENT SPECIFICATION

1. FULL ADDER 4 BIT IC 7483
2. NAND GATE (3 I/P) IC 7410
3. NAND GATE (2 I/P) IC 7400
4. IC TRAINER KIT -
5. PATCH CORDS -

THEORY :

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade,
with the output carry from each full adder connected to the input carry of next
full adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are
designated by subscript numbers from right to left, with subscript 0 denoting the
least significant bits. The carries are connected in chain through the full adder.
The input carry to the adder is C0 and it ripples through the full adder to the
output carry C4.
4 BIT BINARY SUBTRACTOR:
 The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input
carry C0 must be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit
with one common binary adder. The mode input M controls the operation. When
M=0, the circuit is adder circuit. When M=1, it becomes subtractor.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
2-BIT BINARY ADDER
LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR
 TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

BCD to Excess-3 :

BCD Code:
Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-
bit binary code. For example (23)10 is represented by 0010 0011 using BCD code rather
than(10111)2 This code is also known as 8-4-2-1 code as 8421 indicates the binary weights
of four bits(23 , 22 , 21 , 20 ). It is easy to convert between BCD code numbers and the
familiar decimal numbers. It is the main advantage of this code. With four bits, sixteen
numbers (0000 to 1111) can be represented, but in BCD code only 10 of these are used.
The six code combinations (1010 to 1111) are not used and are invalid.

Applications:
Some early computers processed BCD numbers. Arithmetic operations can be performed
using this code. Input to a digital system may be in natural BCD and output may be 7-
segment LEDs.
It is observed that more number of bits are required to code a decimal number using BCD
code than using the straight binary code. However in spite of this disadvantage it is very
convenient and useful code for input and output operations in digital systems.
EXCESS-3 Code:
Excess-3, also called XS3, is a non-weighted code used to express decimal numbers.
It can be used for the representation of multi-digit decimal numbers as can BCD. The code
for each decimal number is obtained by adding decimal 3 and then converting it to a 4-bit
binary number. For e.g. decimal 2 is coded as 0010 + 0011 = 0101 in Excess-3 code.
This is self-complementing code which means 1‘s complement of the coded number
yields 9‘s complement of the number itself. Self-complementing property of this helps
considerably in performing subtraction operation in digital systems, so this code is used for
certain arithmetic operations.

BCD To Excess – 3 Code Conversions:

Convert BCD 2 i. e. 0010 to Excess – 3 codes

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective
code using rules of binary addition.

0010 + 0011 = 0101 – Excess – 3 code for BCD 2

BCD to Excess-3 Truth Table :

Inputs Outputs

B3 B2 B1 B0 E3 (v) E2 (v) E1 (v) E0 (v)

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

Excess-3 to BCD :

The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal
value 3 i.e. 0011 from 4 bit Excess-3 digit.

e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.

0101-0011= 0010- BCD for 2.

Excess-3 to BCD Truth Table :

Inputs Outputs

E3 E2 E1 E0 B3 (v) B2 (v) B1 (v) B0(v)

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1
PROCEDURE :
1. Make the connections as shown in the fig.
2. Pin 14 of all IC’s are connected to +5V and Pin 7 to ground.
3. The inputs are applied at E3, E2, E1 and E0 and the corresponding outputs at B3,
B2, B1and B0 are taken for excess-3 to BCD.
4. B2, B1and B0 are the inputs and the corresponding outputs are E3, E2, E1 and E0
for BCD to excess-3.
5. Repeat the same procedure for other combinations of inputs.
6. Verify the truth table.

CONCLUSION :

In this experiment, Binary 4-bit full adder is studied and verified and obtain the
expression for E3, E2, E1, E0 and for B3, B2, B1, B0.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 4

TITLE : Realization of binary to gray code conversion & vice versa.

AIM : To convert binary to gray code and vice versa.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. X-OR GATE IC 7486
2. PATCH CORD -

THEORY :

Binary Code:
It is straight binary code. The binary number system (with base 2) represents values
using two symbols, typically 0 and 1. Computers call these bits as either off (0) or on (1).
The binary code is made up of only zeros and ones, and used in computers to stand for
letters and digits. It is used to represent numbers using natural or straight binary form.
It is a weighted code since a weight is assigned to every position. Various arithmetic
operations can be performed in this form. Binary code is weighted and sequential code.
Gray Code:
It is a modified binary code in which a decimal number is represented in binary form
in such a way that each Gray- Code number differs from the preceding and the succeeding
number by a single bit. (E.g. for decimal number 5 the equivalent Gray code is 0111 and
for 6 it is 0101. These two codes differ by only one bit position i. e. third from the left.)
Whereas by using binary code there is a possibility of change of all bits if we move from
one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000).
Therefore, it is more useful to use Gray code in some applications than binary code.
The Gray code is a non-weighted code i.e. there are no specific weights assigned to
the bit positions.
Like binary numbers, the Gray code can have any no. of bits. It is also known as
reflected code.
Applications:
1. Important feature of Gray code is it exhibits only a single bit change from one code
word to the next in sequence. This property is important in many applications such as Shaft
encoders where error susceptibility increases with number of bit changes between adjacent
numbers in sequence.
2. It is sometimes convenient to use the Gray code to represent the digital data converted
from the analog data (Outputs of ADC).
3. Gray codes are used in angle-measuring devices in preference to straight forward binary
encoding.
4. Gray codes are widely used in K-map

The disadvantage of Gray code is that it is not good for arithmetic operation

Binary to Gray Conversion :

In this conversion, the input straight binary number can easily be converted to its
Gray code equivalent.
1. Record the most significant bit as it is.
2. EX-OR this bit to the next position bit, record the resultant bit.
3. Record successive EX-ORed bits until completed.
4. Convert 0011 binary to Gray.

Gray to Binary Conversion :

1. The Gray code can be converted to binary by a reverse process.
2. Record the most significant bit as it is.
3. EX-OR binary MSB to the next bit of Gray code and record the resultant bit.
4. Continue the process until the LSB is recorded.
5. Convert 1011 Gray to Binary code.
LOGIC DIAGRAM :

Binary to Gray : Gray to Binary :

Truth Table for Both :

Inputs Outputs
B3 B2 B1 B0 G3 (V) G2 (V) G1 (V) G0 (V)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

PROCEDURE :
1. The circuit connections are made as shown in fig.
2. Pin 14 of all IC’s are connected to +5V and Pin 7 to ground.
3. In the case of Binary to Gray conversion, the inputs B0, B1, B2, and B3 are given
at respective pins and outputs G0, G1, G2, G3 are taken for all the 16 combinations
of the input.
4. In the case of Gray to Binary conversion, the inputs G0, G1, G2, and G3 are given
at respective pins and outputs B0, B1, B2, B3 are taken for all the 16 combinations
of the input.
5. Verify the truth table.

CONCLUSION :
Thus, we have studied the Realization of binary to gray code conversion & vice
versa.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 5

TITLE : MUX/DEMUX – use of 74153, 74139 for arithmetic circuits & code converter.

AIM : To verify the truth table of multiplexer using 74153 & to verify a demultiplexer
using 74139.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. MUX IC 74153
2. DEMUX IC 74139
3. PATCH CORD -

THEORY :

1. The Pin [16] is connected to + Vcc.

2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be
initialized, Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the output and
thus the truth table is verified.
6. In case of half adder using MUX, sum and carry is obtained by applying a
constant inputs at I0a, I1a, I2a, I3a and I0b, I1b, I2b, I3b and the corresponding
values of select lines are changed as per table and the output is taken at Z0a as sum,
and Z0b as carry.
7. In this case the channels A and B are kept at constant inputs according to the table
and the inputs A and B are varied. Making Ea and Eb zero and the output is taken at
Za and Zb.
8. In full adder using MUX, the input is applied at Cn-1 , An and Bn. According to
the table corresponding outputs are taken at Cn and Dn.
PIN CONFIGURATION :

TRUTH TABLE :

CHANNEL – A CHANNEL – B
INPUTS SELECT O/P INPUTS SELECT O/P
LINES LINES
Ēa Ioa I1a I2a I3a S1 S2 Za(v) Ēa Iob I1b I2b I3b S1 S2 Za(v)
1 X X X X X X 0 1 X X X X X X 0
0 0 X X X 0 0 0 0 0 X X X 0 0 0
0 1 X X X 0 0 1 0 1 X X X 0 0 1
0 X 0 X X 0 1 0 0 X 0 X X 0 1 0
0 X 1 X X 0 1 1 0 X 1 X X 0 1 1
0 X X 0 X 1 0 0 0 X X 0 X 1 0 0
0 X X 1 X 1 0 1 0 X X 1 X 1 0 1
0 X X X 0 1 1 0 0 X X X 0 1 1 0
0 X X X 1 1 1 1 0 X X X 1 1 1 1

HALF ADDER USING 74153 HALF SUBTRACTOR

FULL ADDER USING 74153 FULL SUBTRACTOR USING 74153
IC 74139 :
PIN CONFIGURATION :

TRUTH TABLE FOR DEMUX :

CHANNEL – A CHANNEL – B
Inputs Outputs Inputs Outputs
Ēa S1a S0a Y0a Y1a Y2a Y3a Ēb S1b S0b Y0b Y1b Y2b Y3b
1 X X 1 1 1 1 1 X X 1 1 1 1
0 0 0 0 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 1 1 0 0 1 1 0 1 1
0 1 0 1 1 0 1 0 1 0 1 1 0 1
0 1 1 1 1 1 0 0 1 1 1 1 1 0

PROCEDURE :
1. The inputs are applied to either ‘a’ input or ‘b’ input.
2. The demux is activated by making Ea low and Eb low.
3. The truth table is verified.
 HALF ADDER :

HALF SUBTRACTOR :

Half Subtractor
A B Dn (V) Bn (V)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Half Adder
A B Sn (V) Cn (V)
0 0 0 0
FULL ADDER USING IC 74139 :
0 1 1 0
1 0 1 0
1 1 0 1
FULL SUBTRACTOR USING IC 74139 :

CONCLUSION :
In this way we have verified the truth table of multiplexer using 74153 & to verify a
demultiplexer using 74139.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 6

TITLE : Realization of one/two bit comparator and study of 7485 magnitude comparator.
AIM : To verify the truth table of one bit and two bit comparator using logic gates.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. COMPARATOR IC 7485
2. PATCH CORD -

THEORY :
PROCEDURE :
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on Vcc.
4. Applying input and check for outputs.
5. The voltmeter readings of outputs are taken and tabulated in tabular
column.
6. The output are verified.

CONCLUSION :

We have verified the Realization of one/two bit comparator and study of 7485
magnitude comparator.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 7

TITLE : Use of a) Decoder chip to drive LED display & b) Priority encoder.

AIM : To convert a given octal input to the binary output and to study the LED display
using 7447 7-segment decoder/driver.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. 8 TO 3 DECODER IC 74148
2. 7 SEGMENT DECODER IC 7447
3. 7-SEGMENT DISPLAY
4. PATCH CORD -

PIN CONFIGURATION :
PROCEDURE:

A] ENCODER :

1. Connections are made as per circuit diagram.

2. The octal inputs are given at the corresponding pins.
3. The outputs are verified at the corresponding output pins.

B] DECODER :

1. Connections are made as per circuit diagram.

2. Connect the pins of IC 7447 to the respective pins of the LED display board.
3. Give different combinations of the inputs and observe the decimal numbers
displayed on the board.

TABULAR COLUMN :
Q4 Q3 Q2 Q1 O/P Display Glowing LEDs

0 0 0 0 0 a,b,c,d,e,f

0 0 0 1 1 b,c

0 0 1 0 2 a,b,d,e,g

0 0 1 1 3 a,b,c,d,g

0 1 0 0 4 b,c,f,g
 0 1 0 1 5 a,c,d,f,g

0 1 1 0 6 a.c.d.e.f.g

0 1 1 1 7 a.b.c

1 0 0 0 8 a,b,c,d,e,f,g

1 0 0 1 9 a,b,c,d,f,g

1 0 1 0 10 d,e,g

1 0 1 1 11 c,d,g

1 1 0 0 12 c,d,e

1 1 0 1 13 a,g,d

1 1 1 0 14 d,e,f,g

1 1 1 1 15 bl ank

PIN CONFIGURATION :

DISPLAY :

CONCULSION:
The given octal numbers are converted into binary numbers.
The given data is displayed using 7-segment LED decoder.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 8

TITLE : Truth table verification of flip-flops: i) JK Master Slave ii) T type iii) D type.

AIM : To verify the flip-flops: i) JK Master Slave ii) T type iii) D type.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. 3 I/P NAND GATE IC 7410
2. 2 I/P NAND GATE IC 7400

THEORY :

Although JK flip-flop is an improvement on the clocked SR flip-flop it

still suffers from timing problems called "race" if the output Q changes state before
the timing pulse of the clock input has time to go "OFF", so the timing pulse
period (T) must be kept as short as possible (high frequency). As this is sometimes
not possible with modern TTL IC's the much improved Master-Slave J-K Flip-
Flop was developed. This eliminates all the timing problems by using two SR
flip-flops connected together in series, one for the "Master" circuit, which triggers
on the leading edge of the clock pulse and the other, the "Slave" circuit, which
triggers on the falling edge of the clock pulse.

The master-slave JK flip flop consists of two flip flops arranged so that
when the clock pulse enables the first, or master, it disables the second, or slave.
When the clock changes state again (i.e., on its falling edge) the output of the
master latch is transferred to the slave latch. Again, toggling is accomplished by
the connection of the output with the input AND gates.
 Circuit Di agr am: - (M asterSl ave JK Flip-
Flop)

D- Flip flop :
An RS flip-flop is rarely used in actual sequential logic because of its
undefined outputs for inputs R= S= 1. It can be modified to form a more useful
circuit called D flip-flop, where D stands for data. The D flip-flop has only a
single data input D as shown in the circuit diagram. That data input is connected
to the S input of an RS flip-flop, while the inverse of D is connected to the
R input. To allow the flip-flop to be in a holding state, a D-flip flop has a
second input called Enable, EN. The Enable- input is AND-ed with the D-
input.

• When EN=0, irrespective of D-input, the R = S = 0 and the state is held.

• When EN= 1, the S input of the RS flip-flop equals the D input
and R is the inverse of D. Hence, output Q follows D, when
EN= 1.
• When EN returns to 0, the most recent input D is 'remembered'.

D-Flip-Flop:-
PROCEDURE :
1. Connections are made as per circuit diagram.
2. The truth table is verified for various combinations of inputs.

CONCLUSION :
We have verified the truth table of the flip-flops: i) JK Master Slave ii) T type iii)
D type.
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 9

TITLE : Realization of 3-bit counters as a sequential circuit & MOD-N counter design
(7476, 7490, 74192, 74193).

AIM : To verify the Realization of 3-bit counters as a sequential circuit & MOD-N
counter design (7476, 7490, 74192, 74193).

HARDWARE REQUIREMENTS :

IC 7408,

SL No. COMPONENT SPECIFICATI

ON
1. JK FLIP FLOP 7476
2. COUNTER 7490
3. 4 BIT UP/DOWN COUNTER 74192
4. 4 BIT UP/DOWN COUNTER 74193
5. PATCH CORD -

THEORY :

PROCEDURE :
1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA,
QB and QC for IC 7476.
3. Truth table is verified.

PROCEDURE (IC 74192, IC 74193) :

1. Connections are made as per the circuit diagram except the connection from output
of NAND gate to the load input.
2. The data (0011) = 3 is made available at the i/ps A, B, C, D respectively.
3. The load pin made low so that the data 0011 appears at QD, QC, QB & QA
respectively.
4. Now connect the output of NAND gate to the load input.
5. Clock pulses are applied to “count up” pin and the truth table is verified.
6. Now apply (1100) = 12 for 12 to 5 counter and remaining is same as for 3 to 8
counter.
7. The pin diagram of IC 74192 is same as that of 74193. 74192 can be configured to
count between 0 and 9 in either direction. The starting value can be any number
between 0 and 9.
CONCLUSION :
Thus, we have verified the Realization of 3-bit counters as a sequential circuit &
MOD-N counter design (7476, 7490, 74192, 74193).
 Subject : Digital Electronics & Microprocessor Date :
Class : S. Y. B.Tech (Comp) Teacher : J. J. Patil
Student Name : Roll No. :
Experiment No. : 10

TITLE : Writing & testing of sequence generator.

AIM : Design of sequence generator.

HARDWARE REQUIREMENTS :

SL No. COMPONENT SPECIFICATION

1. SHIFT REGISTER IC 7495
2. 2 I/P 4 EX-OR GATE IC 7486
3. PATCH CORD -

THEORY :
A sequence generator is one kind of digital logic circuit. The main function of this is
to generate a set of outputs. Every output is one of a number of binary or Q-ary logic levels
or symbols. The length of the series may be indefinite otherwise fixed. A special kind of
sequence generator is a binary counter. These generators are utilized in a wide variety of
applications like coding & control.

Why Sequence Generator is Required :

The sequence generator circuit is used to generate a prescribed series of bits in

synchronization through a CLK. This kind of generator is used as a code
generator, counters, random bit generators, sequence, and prescribed period generator.
The basic design diagram of this is shown below.

Fig. Sequence Generator Structure

The N-bit shift register outputs like Q0 through QN-1 are applied like the inputs to
a combinational circuit is known as the next state decoder. Here, the output of a next state
decoder ‘Y’ is given as the serial input to the shift register. The designing of the next state
decoder is done based on the sequence required.
CIRCUIT DIAGRAM SEQUENCE GENERATOR :

TRUTH TABLE :
Map
Clock QA QB QC QD o/p D
Value
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1

DESIGN :
To generate the sequence of length S it is necessary to use at least N number
of Flip Flops, which satisfies the condition S<=2N -1.
The given sequence length S= 15.
Therefore N = 4.

NOTE : There is no guarantee that the given sequence can be generated by 4 f/fs. If the
sequence is not realizable by 4 f/fs then 5 f/fs must be used and so on.

PROCEDURE :
1. Connections are made as per the circuit diagram.
2. Clock pulses are applied one by one and truth table is verified.

CONCLUSION :
We have studied the design of sequence register.