Subject Name/code: 3CS4-24 Digital Electronics Lab Practical hrs- 3

Class:B.tech. II Yr. III Sem. Computer Science Engineering & Information Tech.

1. Syllabus:
S.No. Contents

1 To verify the truth tables of basic logic gates: AND, OR, NOR, NAND, NOR. Also
to verify the truth table of Ex-OR, Ex-NOR (For 2, 3, & 4 inputs using gates with 2,
3, & 4 inputs).

2 To verify the truth table of OR, AND, NOR, Ex-OR, Ex-NOR realized using
NAND & NOR gates.

3 To realize an SOP and POS expression.

4 To realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR
gates and to verify their truth tables.

5 To realize a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor &
basic Full Adder/ Subtractor.

6 To verify the truth table of 4-to-1 multiplexer and 1-to-4 demultiplexer. Realize the
multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and 1-
to-8demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4 demultiplexer.

7 Design & Realize a combinational circuit that will accept a 2421 BCD code and
drive a TIL -312 seven-segment display.

8 Using basic logic gates, realize the R-S, J-K and D-flip flops with and without
clock signal and verify their truth table.

9 Construct a divide by 2, 4 & 8 asynchronous counter. Construct a 4-bit binary

counter and ring counter for a particular output pattern using D flip flop.

10 Perform input/output operations on parallel in/Parallel out and Serial in/Serial out
registers using clock. Also exercise loading only one of multiple values into the
register using multiplexer.

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2. Course Objectives:
1. To provide students basic experimental experiences in the operation of various families of
digital circuits.
2. To introduce the concepts and techniques associated with the number systems and codes.
To minimize the logical expressions using Boolean postulates.
3. To analyze and design digital combinational circuits like decoders, encoders, multiplexers,
and de-multiplexers including arithmetic circuits (half adder, full adder, multiplier).
4. To analyze sequential digital circuits like flip-flops, registers, counters.
5. To impart the concepts of digital electronics practically and train students with all the
equipments which will help in improving the basic knowledge.

3. Programme Outcomes (POs):

(a) An ability to apply knowledge of mathematics, science, and engineering.

(b) An ability to design and conduct experiments, as well as to analyze and interpret data.
(c) An ability to design a system, component, or process to meet desired needs within
realistic constraints such as economic, environmental, social, political, ethical, health and
safety, manufacturability, and sustainability.
(d) An ability to function on multidisciplinary teams.
(e) An ability to identify, formulate, and solve engineering problems.
(f) An understanding of professional and ethical responsibility.
(g) An ability to communicate effectively. The broad education necessary to understand the
impact of engineering solutions in a global, economic, environmental, and societal
context.
(h) Recognition of the need for, and an ability to engage in life-long learning.
(i) Knowledge of contemporary issues.
(j) An ability to use the techniques, skills, and modern engineering tools necessary for
engineering practice.
(l) Graduates will possess strong fundamental concepts on database technologies, Operating
systems, advanced programming, Software engineering.
(m) Graduates will demonstrate with an ability to design, develop, test, debug, deploy,
analyze, troubleshoot, maintain, manage and secure the software.
(n) A knowledge of institutions/organizations/companies related to computer science
engineering in surrounding areas.

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 3. Course outcomes :
After completion of this lab course students will be able to
1) Design digital circuits with basic logic gates to meet a set of specifications.
2) Construct and analyze digital circuits in different forms.
3) Analyze and design digital combinational circuits like decoders, encoders, multiplexers, and
de-multiplexers including arithmetic circuits (half adder, full adder, multiplier).
4) Analyze sequential digital circuits like flip-flops(R-S,J-K and D-flip-flops) and
counters(Asynchronous and ring counters).
5) Perform input/output operations on parallel in/Parallel out and Serial in/Serial out registers
using clock and various register operations which are building blocks of RAM/ROM.
6) Understand the importance and need for verification, testing of digital logic and design for
testability.

4. Mapping of course outcomes with POs:

Pos a b c d e f g H i j k l m n
Cos
1 √ √ √ √ √ √ √ √ √
2 √ √ √ √ √ √ √ √ √ √
3 √ √ √ √ √
4 √ √ √ √ √ √ √ √
5 √ √ √ √ √ √ √ √
6 √ √ √ √ √ √ √

5. Beyond Syllabus Experiments

1. To study and design Binary to Gray code converter.
2. To implement circuit for 3-to-8 Decoder

6. Mapping of beyond syllabus experiments with POs:

Pos a b c d e f g h i j k l m n
Beyond
Syllabus
Exp.
1 √ √ √ √
2 √ √ √ √ √ √

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 EXPERIMENT NO-1

AIM: To verify the truth tables of basic logic gates: AND, OR, NOR, NAND, NOR. Also to
verify the truth table of Ex-OR, Ex-NOR (For 2, 3, & 4 inputs using gates with 2, 3, & 4 inputs).

APPARATUS/COMPONENTS REQUIRED:

S.No. COMPONENT SPECIFICATION

1. AND GATE IC 7408
2. X-OR GATE IC 7486
3. NOT GATE IC 7404
4. OR GATE IC 7432
5. NAND GATE IC 7400
6. NOR GATE IC 7402
7. 3 I/P AND GATE IC 7411
8. 3 I/P NOR GATE IC 7427
9. 4 I/P NAND GATE IC 7420
10. 4 I/P NOR GATE IC 7425
11. IC TRAINER KIT -
12. WIRES -

THEORY:

Logic gates are the basic components in digital electronics. They are used to create digital circuits
and even complex integrated circuits. For example, complex integrated circuit may bring already a
complete circuit ready to be used – microprocessors and microcontrollers are the best example – but
inside them they were projected using several logic gates.
A gate is a digital electronic circuit having only one output but one or more inputs. The output or a
signal will appear at the output of the gate only for certain input-signal combinations. There are many
types of logic gates; such as AND, OR and NOT, which are usually called the three basic gates.
Other gates are the NAND and the NOR gates; which are simply combinations of an AND or an OR
gate with a NOT gate inserted just before the output signal. Other gates include the XOR “Exclusive-
OR”and the XNOR "Exclusive NOR" gates.
All the logic gates used in the exercises below are known as TTL (transistor-to-transistor) Logic.
These have the convenient property that the output of any gate can be used directly as input to
anothergate. All these TTL circuits are operated from a 5 V power supply, and the binary digits 0 and
1 are represented by low and high voltages on the gate terminals.

(1) The Logic "AND" Gate

A Logic AND Gate is a type of digital logic gate that has an output which is normally at logic
level "0" and only goes "HIGH" to a logic level "1" when ALL of its inputs are at logic level
"1". The output of a Logic AND Gate only returns "LOW" again when ANY of its inputs are at
a logic level "0". The logic or Boolean expression given for a logic AND gate is that for Logical

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Multiplication which is denoted by a single dot or full stop symbol, (.) giving us the Boolean
expression of: A.B = Q.

Then we can define the operation of a 2-input logic AND gate as being:"If both A and B are true,
then Q is true"

2-Input Transistor AND Gate

A simple 2-input logic AND gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Both transistors must be saturated "ON" for an output at Q.

The Digital Logic "AND" Gate

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Commonly available digital logic AND gate IC's include:

TTL Logic Types CMOS Logic Types

 74LS08 Quad 2-input  CD4081 Quad 2-input

 74LS11 Triple 3-input  CD4073 Triple 3-input
 74LS21 Dual 4-input  CD4082 Dual 4-input

Quad 2-input AND Gate 7408

(2)The Logic "OR" Gate

A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which is
normally at logic level "0" and only goes "HIGH" to a logic level "1" when ANY of its inputs are
at logic level "1". The output of a Logic OR Gate only returns "LOW" again when ALL of its
inputs are at a logic level "0". The logic or Boolean expression given for a logic OR gate is that
for Logical Addition which is denoted by a plus sign, (+) giving us the Boolean expression
of: A+B = Q.

Then we can define the operation of a 2-input logic OR gate as being:

"If either A or B is true, then Q is true"

2-input Transistor OR Gate

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A simple 2-input logic OR gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Either transistor must be saturated "ON" for an output at Q.

Logic OR Gates are available using digital circuits to produce the desired logical function and is given a
symbol whose shape represents the logical operation of the OR gate.

The Digital Logic "OR" Gate

Commonly available OR gate IC's include:

TTL Logic Types CMOS Logic Types

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  74LS32 Quad 2-input  CD4071 Quad 2-input
 CD4075 Triple 3-input
 CD4072 Dual 4-input

Quad 2-input OR Gate 7432

(3)The Digital Logic "NOT" Gate

The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes referred
to as an Inverting Buffer or simply a Digital Inverter. It is a single input device which has an
output level that is normally at logic level "1" and goes "LOW" to a logic level "0" when its
single input is at logic level "1", in other words it "inverts" (complements) its input signal. The
output from a NOT gate only returns "HIGH" again when its input is at logic level "0" giving us
the Boolean expression of: A = Q.

Then we can define the operation of a single input logic NOT gate as being:

"If A is NOT true, then Q is true"

Transistor NOT Gate

A simple 2-input logic NOT gate can be constructed using a RTL Resistor-transistor switches as
shown below with the input connected directly to the transistor base. The transistor must be
saturated "ON" for an inversed output "OFF" at Q.

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Logic NOT Gates are available using digital circuits to produce the desired logical function. The
standard NOT gate is given a symbol whose shape is of a triangle pointing to the right with a
circle at its end. This circle is known as an "inversion bubble" and is used in NOT, NAND and
NOR symbols at their output to represent the logical operation of the NOT function. This bubble
denotes a signal inversion (complementation) of the signal and can be present on either or both
the output and/or the input terminals.

The Digital Inverter or NOT gate

Then, with an input voltage at "A" HIGH, the output at "Q" will be LOW and an input voltage at
"A" LOW the resulting output voltage at "Q" is HIGH producing the complement of the input
signal.

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Commonly available logic NOT gate and Inverter IC's include

TTL Logic Types CMOS Logic Types

 74LS04 Hex Inverting NOT  CD4009 Hex Inverting

Gate NOT Gate
 74LS04 Hex Inverting NOT  CD4069 Hex Inverting
Gate NOT Gate
 74LS14 Hex Schmitt Inverting
NOT Gate
 74LS1004 Hex Inverting
Drivers

Inverter or NOT Gate 7404

(4)The Logic "NAND" Gate

The Logic NAND Gate is a combination of the digital logic AND gate with that of an inverter or
NOT gate connected together in series. The NAND (Not - AND) gate has an output that is
normally at logic level "1" and only goes "LOW" to logic level "0" when ALL of its inputs are at
logic level "1". The Logic NAND Gate is the reverse or "Complementary" form of the AND
gate we have seen previously.

Logic NAND Gate Equivalence

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The logic or Boolean expression given for a logic NAND gate is that for Logical Addition, which
is the opposite to the AND gate, and which it performs on the complements of the inputs. The
Boolean expression for a logic NAND gate is denoted by a single dot or full stop symbol, (.) with
a line or Overline, ( ‾‾ ) over the expression to signify the NOT or logical negation of the NAND
gate giving us the Boolean expression of: A.B = Q. Then we can define the operation of a 2-
input logic NAND gate as being:

"If either A or B are NOT true, then Q is true"

Transistor NAND Gate

A simple 2-input logic NAND gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Either transistor must be cut-off "OFF" for an output at Q.

Logic NAND Gates are available using digital circuits to produce the desired logical function
and is given a symbol whose shape is that of a standard AND gate with a circle, sometimes
called an "inversion bubble" at its output to represent the NOT gate symbol with the logical
operation of the NAND gate given as.

The Digital Logic "NAND" Gate

2-input NAND Gate

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Commonly available logic NAND gate IC's include:

TTL Logic Types CMOS Logic Types

 74LS00 Quad 2-input  CD4011 Quad 2-input

 74LS10 Triple 3-input  CD4023 Triple 3-input
 74LS20 Dual 4-input  CD4012 Dual 4-input
 74LS30 Single 8-input

Quad 2-input NAND Gate 7400

(5)The Logic "NOR" Gate

The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR gate with
that of an inverter or NOT gate connected together in series. The NOR (Not - OR) gate has an
output that is normally at logic level "1" and only goes "LOW" to logic level "0" when ANY of

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its inputs are at logic level "1". The Logic NOR Gate is the reverse or "Complementary" form of
the OR gate we have seen previously.

NOR Gate Equivalent

The logic or Boolean expression given for a logic NOR gate is that for Logical Multiplication
which it performs on the complements of the inputs. The Boolean expression for a logic NOR
gate is denoted by a plus sign, (+) with a line or Overline, ( ‾‾ ) over the expression to signify the
NOT or logical negation of the NOR gate giving us the Boolean expression of: A+B = Q.

Then we can define the operation of a 2-input logic NOR gate as being:

"If both A and B are NOT true, then Q is true"

Transistor NOR Gate

A simple 2-input logic NOR gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Both transistors must be cut-off "OFF" for an output at Q.

Logic NOR Gates are available using digital circuits to produce the desired logical function and is given
a symbol whose shape is that of a standard OR gate with a circle, sometimes called an "inversion bubble"
at its output to represent the NOT gate symbol with the logical operation of the NOR gate given as.The

Digital Logic "NOR" Gate

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 Commonly available NOR gate IC's include:

TTL Logic Types CMOS Logic Types

 74LS02 Quad 2-input  CD4001 Quad 2-input

 74LS27 Triple 3-input  CD4025 Triple 3-input
 74LS260 Dual 4-input  CD4002 Dual 4-input

Quad 2-input NOR Gate 7402

(6)The Exclusive-OR Gate

The output of an Exclusive-OR gate ONLY goes "HIGH" when its two input terminals are at
"DIFFERENT" logic levels with respect to each other and they can both be at logic level "1" or
both at logic level "0" giving us the Boolean expression of: Q = A’B + AB’. The Exclusive-OR
Gate function is achieved is achieved by combining standard gates together to form more
complex gate functions. An example of a 2-input Exclusive-OR gate is given below.

The Digital Logic "Ex-OR" Gate

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2-input Ex-OR Gate

TTL Logic Types CMOS Logic Types

 74LS86 Quad 2-input  CD4030 Quad 2-input

Quad 2-input Ex-OR Gate 7486

(7)The Exclusive-NOR Gate

The output of an Exclusive-NOR gate ONLY goes "HIGH" when its two input terminals, A and
B are at the "SAME" logic level which can be either at a logic level "1" or at a logic level "0".
Then this type of gate gives and output "1" when its inputs are "logically equal" or "equivalent"
to each other, which is why an Exclusive-NOR gate is sometimes called an Equivalence Gate.

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Ex-NOR Gate Equivalent

The logic function implemented by a 2-input Ex-NOR gate is given as "when both A AND B are
the SAME" will give an output at Q. In general, an Exclusive-NOR gate will give an output
value of logic "1" ONLY when there are an EVEN number of 1's on the inputs to the gate (the
inverse of the Ex-OR gate) except when all its inputs are "LOW". Commonly available
Exclusive-NOR gate IC's include:

Quad 2-input Ex-NOR Gate 74266

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3-INPUT GATE ICs:

4 INPUT GATE ICs:

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RESULT: Logic gates are studied and all the gates are verified.

CONCLUSION: Successfully verify the truth table of logic gate.

PRECAUTIONS:
1. All the connections should be made properly.
2. IC should not be reversed.
3. It should be care that the values of the components of the circuit is does not exceed
to their ratings (maximum value).
4. Before the circuit connection it should be check out working condition of all the
Component.

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 EXPERIMENT NO-2

AIM: To verify the truth table of OR, AND, NOR, Ex-OR, Ex-NOR realized using NAND
& NOR gates.

APPARATUS REQUIRED: Digital Trainer Kit, IC 7400,IC 7402,Connecting wires/cords.

THEORY: Logic gates like NAND and NOR are also used in the design of digital circuits.

NAND Gate:
The NAND gate represents the complement of the AND operation. Its name is an abbreviation of
NOT AND.When all the inputs are HIGH, the output is LOW. If any one or both the inputs are
LOW, then the output is HIGH.
The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the
output, denoting that a complement operation is performed on the output of the AND gate.Also
the NAND gate is equivalent to an OR gate with the bubble at its inputs.

Fig.2.1. The truth table and the graphic symbol of NAND gate

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NOR Gate:
The NOR gate represents the complement of the OR operation. Its name is an abbreviation of
NOT OR.
When all the inputs are LOW, the output is HIGH. If any one or both the inputs are HIGH, then the
output is LOW.
The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output,
denoting that a complement operation is performed on the output of the OR gate.Also The NOR
gate is equivalent to an AND gate with the bubble at its inputs.

Fig.2.2. The truth table and the graphic symbol of NOR gate

Universal Gates:
A universal gate is a gate which can implement any Boolean function without need to use any
other gate type.The NAND and NOR gates are universal gates.
In fact, an AND gate is typically implemented as a NAND gate followed by an inverter.
Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter.

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Designing the Solution:
NAND Gate as a Universal Gate:
To prove that any Boolean function can be implemented using only NAND gates, we will show
that the AND, OR,NOT,X-OR,X-NOR operations can be performed using only these gates.

 Implementing an Inverter Using only NAND Gate

The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’.

2. One NAND input pin is connected to the input signal A while all other input pins are
connected to logic 1. The output will be A’.

 Implementing AND Using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by
a NAND gate with its output complemented by a NAND gate inverter).

 Implementing OR Using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by
a NAND gate with all its inputs complemented by NAND gate inverters).

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  Implementing EXOR Using only NAND Gates

 Implementing EX-NOR Using only NAND Gates

NOR Gate as a Universal Gate:

To prove that any Boolean function can be implemented using only NOR gates, we will show
that the AND, OR, NOT ,EXOR and EXNOR operations can be performed using only these
gates.

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  Implementing an Inverter Using only NOR Gate
The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

1. All NOR input pins connect to the input signal A gives an output A’.

2. One NOR input pin is connected to the input signal A while all other input pins are connected
to logic 0. The output will be A’.

 Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a
NOR gate with its output complemented by a NOR gate inverter)

 Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced
by a NOR gate with all its inputs complemented by NOR gate inverters)

 Implementing EXOR Using only NOR Gates

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  Implementing EXNOR Using only NOR Gates

Equivalent Gates:
The shown figure summarizes important cases of gate equivalence. Note that bubbles indicate a
complement operation (inverter).

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A NAND gate is equivalent to an inverted-input OR gate.

An AND gate is equivalent to an inverted-input NOR gate.

A NOR gate is equivalent to an inverted-input AND gate.

An OR gate is equivalent to an inverted-input NAND gate.

Two NOT gates in series are same as a buffer because they cancel each other as A’’ = A.

 .

 Basic IC needed are NAND gate and NOR gate,IC diagram are given as below:

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 Fig.2.3 – Pin Diagram of NAND & NOR GATES

RESULT: Designing of basic gates by using of NAND and NOR gate is successfully done .

CONCLUSION: A universal gate is a gate which can implement any Boolean function without
need to use any other gate type. Hence all the gates are realized using Universal gates.

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 EXPERIMENT NO-3

AIM: To realize SOP and POS expressions

APPARATUS/COMPONENTS REQUIRED: Digital Trainer Kit, IC’s, Connecting

wires/cords.

THEORY: We have seen before those Boolean functions in either Sum of Product (SOP) or
Product of Sum (POS) forms can be implemented using 2-Level implementations.
For SOP forms AND gates will be in the first level and a single OR gate will be in the second
level. For POS forms OR gates will be in the first level and a single AND gate will be in the
second level. Note that using inverters to complement input variables is not counted as a level.

SOP: A minterm, for a function of n variables, is a product term in which each of the n variables
appears once. Each variable in the minterm may appear in its complemented or un
complemented form. Any function F can be represented by a sum of minterms, where each
minterm is ANDed with the corresponding value of the output for F.
Implement the following SOP function
F1=Y' + X'YZ' + XY

Being an SOP expression, it is implemented in 2-levels as shown in the figure.

Product Term = Logical ANDing of literals

Sum = Logical ORing of product terms

POS: A Maxterm, for a function of n variables, is a sum term in which each of the n variables
appears once. Each variable in the Maxterm may appear in its complemented or un
complemented form. Any function F can be represented by a product of Maxterms, where each
Maxterm is ANDed with the complement of the corresponding value of the output for F.

Implement the following POS function

F2=X.(Y' + Z).(X' + Y + Z)

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Sum Term = Logical ORing of variables
Product = Logical ANDing of sum terms
There are some other types of 2-level combinational circuits which are
  NAND-AND 
  AND-NOR, 
 NOR-OR, 
 OR-NAND 

AND-NOR functions:
Implement the following function
F  XZ YZ  XYZ or
F  XZ Y Z  XYZ
Since F’ is in SOP form, it can be implemented by using NAND-NAND circuit.
By complementing the output we can get F, or by using NAND-AND circuit as shown in the
figure.

OR-NAND functions:
Implement the following function
F (X Z).(Y Z).(X Y Z) or
F (X  Z)(Y  Z)(X Y  Z)

Since F’ is in POS form, it can be implemented by using NOR-NOR circuit.

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By complementing the output we can get F, or by using NOR-OR circuit as shown in the figure.

It can also be implemented using OR-NAND circuit as it is equivalent to NOR-OR circuit as

shown in the figure.

RESULT: Hence both SOP and POS forms of expression are verified.

PRECAUTIONS:
1) The continuity of the connecting terminals should be checked before going
2) It should be care that the values of the components of the circuit is does not exceed
to their ratings (maximum value).

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 EXPERIMENT NO-4

AIM: To realize half adder or Subtractor & Full Adder or Subtractor using NAND &
NOR gates and to verify their truth table.

APPARATUS/COMPONENTS REQUIRED: Trainer kit, Digital IC’s7400,7402,

connecting wires/ cords.

THEORY: Another common and very useful combinational logic circuit which can be
constructed using just a few basic logic gates and adds together binary numbers is the Binary
Adder circuit. The Binary Adder is made up from standard AND and Ex-OR gates and allow us
to "add" together single bit binary numbers, a and b to produce two outputs, the SUM of the
addition and a CARRY called the Carry-out, ( Cout ) bit. One of the main uses for the Binary
Adder is in arithmetic and counting circuits.

The Half Adder Circuit

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry
signal from the addition of the less significant bits sum from the X-OR Gate the carry out from
the AND gate.

Truth Table:

K map:

SUM = A’B + AB’ CARRY = AB

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Logic Diagram:

From the K map we can see that the SUM (S) output is the result of the Ex-OR gate and the
Carry-out (Cout) is the result of the AND gate. One major disadvantage of the Half Adder circuit
when used as a binary adder, is that there is no provision for a "Carry-in" from the previous
circuit when adding together multiple data bits. For example, suppose we want to add together
two 8-bit bytes of data, any resulting carry bit would need to be able to "ripple" or move across
the bit patterns starting from the least significant bit (LSB). The most complicated operation the
half adder can do is "1 + 1" but as the half adder has no carry input the resultant added value
would be incorrect. One simple way to overcome this problem is to use a Full Adder type binary
adder circuit.

Fig. 4.1 Circuit diagram for half-adder using

NAND gates. Fig. 4.2 Circuit diagram for half-adder using
NOR gates
.

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The Full Adder Circuit: The main difference between the Full Adder and the previous seen
Half Adder is that a full adder has three inputs, the same two single bit binary inputs A and B as
before plus an additional Carry-In (C-in) input as shown below. The 1-bit Full Adder circuit
above is basically two half adders connected together and consists of three Ex-OR gates, two
AND gates and an OR gate, six logic gates in total.

Truth Table:

K map:

SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC

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LOGIC DIAGRAM:

Fig.4.3- Full Adder implementation using NAND Gate

Fig.4.4- Full Adder implementation using NOR Gate

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The Half Subtractor Circuit

A half-subtractor has two inputs and two outputs. Let the input variables minuend and
subtrahend be designated as A and B respectively, and output functions be designated as D for
difference and B for borrow. The truth table of the functions is as follows.

By considering the minterms of the truth table, the Boolean expressions of the outputs D and B
functions can be written as

Di = A′B + AB′ Bo = A′B.

Fig.4.5 The logic diagram to realize the half-subtractor circuit.

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 Fig.4.6 The logic diagram to realize the half-subtractor circuit using NAND gate

The Full Subtractor Circuit

A combinational circuit of full-subtractor performs the operation of subtraction of three bits—the

minuend, subtrahend, and borrow generated from the subtraction operation of previous
significant digits and produces the outputs difference and borrow. Let us designate the input
variables minuend as A, subtrahend as B, and previous borrow as C, and outputs difference as D
and borrow as BORout. Eight different input combinations are possible for three input variables.

Truth table for Full subtractor:

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The simplified Boolean expressions of the outputs are

D = A′B′C +A′BC′ + AB′C′ + ABC BORout = A′C + A′B + BC.

The logic diagram for the above functions is shown in Figure 6.

Fig.4.7 The logic diagram to realize the full-subtractor circuit.

Fig.4.8 The logic diagram to realize the full-subtractor circuit using NAND gate

RESULT:.The truth table for Half adder/Subtractor and Full Adder/Subtractor has been verified.

CONCLUSION: By using various logic gate ICs we can perform the full or half adder and
subtractor and check the truth table

36
 EXPERIMENT NO-5

AIM:To realize a 4-bit ripple adder/Subtractor using basic full adder/ Subtractor

APPARATUS/COMPONENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATIO QTY.

N
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER - 1
KIT
4. WIRES - AS REQUIRED

THEORY:

In digital circuits, an adder–subtractor is a circuit that is capable of adding or subtracting

numbers (in particular, binary). Below is a circuit that does adding or subtracting depending on a
control signal. It is also possible to construct a circuit that performs both addition and subtraction
at the same time.

4 BIT BINARY ADDERS:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend
bits of ‘B’ are designated by subscript numbers from right to left, with subscript 0 denoting the
least significant bits. The carries are connected in chain through the full adder. The input carry to
the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data
input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1 when
performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit.
When M=1, it becomes subtractor.

37
PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM: 4-BIT BINARY ADDER

LOGIC DIAGRAM for 4-BIT BINARY SUBTRACTOR:

38
LOGIC DIAGRAM FOR 4-BIT BINARY ADDER/SUBTRACTOR:

RESULT: Thus the 4-bit adder and subtractor using IC 7483 was designed and implemented.

CONCLUSION: For various combinations of selected input lines, observed the LED output and
verified the truth table.

PRECAUTIONS:
1. All ICs should be checked before starting the experiment.
2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.

39
 EXPERIMENT NO-6

AIM : Design 4:1 mux and 1:4 demux with basic logic gate also construct 8:1 mux and 1:8
demux using blocks of 4:1mux and 1:4 demux.

APPARATUS/COMPONENTS REQUIRED: Trainer kit, Basic logic

gatesIC(7404,7411,7432), ICs 74153,74138,74155, Connecting wires/leads.

THEORY:

MULTIPLEXER:
Combinational logic switching devices that operate like a very fast acting multiple position
rotary A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", are
switch. They connect or control, multiple input lines called "channels" consisting of either 2, 4, 8
or 16 individual inputs, one at a time to an output. Then the job of a multiplexer is to allow
multiple signals to share a single common output.

Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. Normally there are 2n input line and n selection
lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is
also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4
demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines
enable only one gate at a time and the data on the data input line will pass through the selected
gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

40
Logic diagram for 4-to-1multiplexer:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 I0
0 1 I1
1 0 I2
1 1 I3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

41
FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

8-to-1 MUX using Two 4-to- 1 Multiplexers

42
Block diagram for 8:1 multiplexer:

1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

When the application requires a large demultiplexer with more number of output pins, then we
cannot implement by a single integrated circuit. In case if more than 16 output pins are needed,
then two or more demultiplexer ICs are cascaded to fulfill the requirement. Consider the case
that a 1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a proper
cascading.

43
Pin Diagram for 74138(Demux)

44
 PIN DIAGRAM FOR IC 74155:DEMUX

RESULT: Thus 4:1 mux and 1:4 demux are designed using basic gates and their truth tables are
verified.
CONCLUSION: The multiplexer and demultiplexer was also designed USING IC 74153 , IC
74138,IC 74155 and verified the truth table.

PRECAUTIONS:

1. All ICs should be checked before starting the experiment.

2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.

45
 EXPERIMENT NO-7

AIM :Design and realize a combinational circuit that will accept the 2421 BCD code and
drive a Til-312 to 7-Segment Display

APPARATUS REQUIRED: Digital I.C.7447, Trainer kit, connecting wires

THEORY:

The Binary Coded Decimal (BCD) to 7-Segment Display Decoder. 7-segment LED (Light
Emitting Diode) or LCD (Liquid Crystal) displays, provide a very convenient way of displaying
information or digital data in the form of numbers, letters or even alpha-numerical characters and
they consist of 7 individual LED's (the segments), within from 0 to 9 and A to F respectively, on
the display the correct combination of LED segments need to be illuminated and BCD to 7-
segment Display Decoders such as the 74LS47 do just that. A standard 7-segment LED display
generally has 8 input connections, one for each LED segment and one that acts as a common
terminal or connection for all the internal segments.

There are two important types of 7-segment LED digital display.

 The Common Cathode Display (CCD) - In the common cathode display, all the cathode
connections of the LED's are joined together to logic "0" and the individual segments are
illuminated by application of a "HIGH", logic "1" signal to the individual Anode
terminals.

 The Common Anode Display (CAD) - In the common anode display, all the anode
connections of the LED's are joined together to logic "1" and the individual segments are
illuminated by connecting the individual Cathode terminals to a "LOW", logic "0" signal.

7-Segment Display Format

46
 7-Segment Display Elements for all Numbers.

It can be seen that to display any single digit number from 0 to 9 or letter from A to F, we would
need 7 separate segment connections plus one additional connection for the LED's "common"
connection. Also as the segments are basically a standard light emitting diode, the driving circuit
would need to produce up to 20mA of current to illuminate each individual segment and to
display the number 8, all 7 segments would need to be lit resulting a total current of nearly
140mA, (8 x 20mA). Obviously, the use of so many connections and power consumption is
impractical for some electronic or microprocessor based circuits and so in order to reduce the
number of signal lines required to drive just one single display, display decoders such as the
BCD to 7-Segment Display Decoder and Driver IC's are used instead.

2421 CODES:

The 2421 code utilizes weighted binary codes with 4 bits.Weighted binary codes are of the form:
A3B3 + A2B2 + A1B1 + A0B0
The terms in ‘B’ are referred to as Code Weights and those in ‘A’ are the binary codes. Note that
since 2 + 4 + 2 + 1 = 9, only the number set 0 – 9 can be represented in each 4 bits.The
conversion from 2421 code can also be done by:
2B3 + 4B2 + 2B1 + 1B0 = Base 10 equivalent ,the co-efficient 2,4,2,1 are called the code
weights. Using 4 bits and binary representations, there are 16 possible combinations. However,
the 2421 system only utilizes 10 distinct combinations, leaving 6 illegal combinations. This
property allows for error detection in a system. The 2421 code is self-complementing, meaning
that the code word for the 9’s complement of any digit may be obtained by complementing the
individual bits of the 2421 code word.

Binary Coded Decimal

Binary Coded Decimal (BCD or "8421" BCD) numbers are made up using just 4 data bits (a
nibble or half a byte) BCD numbers only range from 0 to 9, with the binary number patterns of
1010 through to 1111 (A to F) being invalid inputs for this type of display and so are not used as
shown below.

47
Design a combinational circuit for converting 2421 code to BCD code.

Both the 2421 code and BCD code are 4-bit codes and represent the decimal equivalents 0 to 9.
To design the converter circuit for the above, first the truth table is prepared with the input
variables W, X, Y, and Z of 2421 code, and the output variables A, B, C, and D. Karnaugh maps
to obtain the simplified expressions of the output functions are shown in Figure. Unused
combinations are considered as don’t-care condition.

Decimal 2421 INPUT BCD OUTPUT

Equivalent W X Y Z A B C D
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 1 0 1 1 0 1 0 1
6 1 1 0 0 0 1 1 0
7 1 1 0 1 0 1 1 1
8 1 1 1 0 1 0 0 0
9 1 1 1 1 1 0 0 1

48
K map:
Y′Z
Y′Z′ Y′Z YZ YZ′
′ Y′Z YZ YZ′
W′X
W′X
′
′

W′X X X X
W′X 1 X X X

WX 1 1
WX 1 1

WX′ X X X
WX′ X X 1 X
(a) Karnaugh map for A.

(b) Karnaugh map for B.

Y′Z′ Y′Z YZ YZ′

W′X Y′Z′ Y′Z YZ YZ′
′ 1 1 W′X
′ 1 1
W′X X X X
W′X X X X
WX 1 1
WX 1 1
WX′ X X X
WX′ X X 1 X
(c) Karnaugh map for C.

(d) Karnaugh map for D.

Logic Diagram for 2421 to BCD code conversion

49
BCD to 7-Segment Display Decoders

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or
74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller
4-bit binary number (half a byte) to be used to display all the digital numbers from 0 to 9 and by
adding two displays together; a full range of numbers from 00 to 99 can be displayed with just a
single byte of 8 data bits.

The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits) of data,
allowing a single data byte to hold a BCD number in the range of 00 to 99.

PIN diagram for 7447 IC:

50
RESULT: Hence the truth table for BCD to 7-Segment converter is verified.

PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

51
 EXPERIMENT NO-8

AIM :Using basic logic gates ,realize the R-S, J-k and D flip flops with and without clock
pulse and verify truth table.

APPARATUS/COMPONENTS REQUIRED: Power supply, Digital Trainer kit, ICs – 7474,

Connecting wires, Multimeter,CRO, Pulse Generator, Patch Chords, IC 7400 NAND gate IC, IC
7402 NOR gate IC, IC 7404 NOT gate IC,7474,7476 IC, LED.

THEORY:

Sequential Logic circuits have some form of inherent "Memory" built in to them as they are able
to take into account their previous input state as well as those actually present, a sort of "before"
and "after" is involved with sequential circuits.

In other words, the output state of a sequential logic circuit is a function of the following three
states, the "present input", the "past input" and/or the "past output". Sequential Logic circuits
remember these conditions and stay fixed in their current state until the next clock signal changes
one of the states, giving sequential logic circuits "Memory".

Sequential logic circuits are generally termed as two state or Bistable devices which can have
their output or outputs set in one of two basic states, a logic level "1" or a logic level "0" and will
remain "latched" (hence the name latch) indefinitely in this current state or condition until some
other input trigger pulse or signal is applied which will cause the bistable to change its state once
again.

Sequential Logic Representation

The word "Sequential" means that things happen in a "sequence", one after another and in
Sequential Logic circuits, the actual clock signal determines when things will happen next.
Simple sequential logic circuits can be constructed from standard Bistable circuits such as Flip-
flops, Latches and Counters and which themselves can be made by simply connecting together
universal NAND Gates and/or NOR Gates in a particular combinational way to produce the
required sequential circuit.

52
FLIP-FLOP:-

"Flip-flop" is the common name given to two-state devices which offer basic memory for
sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and
are commonly used in banks called "register" for the storage of binary numerical data.

1.The basic Flip Flop or S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch.

 S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q’. The diagram and truth table is shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0—Q=1, Q’=0

This state is also called the SET state.

53
S=0, R=1—Q=0, Q’=1

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the value of S.

S=0, R=0—Q & Q’ = Remember

If both the values of S and R are switched to 0, then the circuit remembers the value of S and R
in their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided.

 S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown

below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

54
S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S and R
in their previous state.

 Clocked S-R Flip Flop

It is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem
can be overcome by using a bistable SR flip-flop that can change outputs when certain invalid
states are met, regardless of the condition of either the Set or the Reset inputs. For this, a clocked
S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop.

A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is
’0′, the outputs of both the AND Gates remain ’0′. As soon as a pulse is given the value of CP
turns ’1′. This makes the values at S and R to pass through the NOR Gate flip flop. But when the
values of both S and R values turn ’1′, the HIGH value of CP causes both of them to turn to ’0′
for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it depends on whether the set or reset input of
the flip-flop remains a ’1′ longer than the transition to ’0′ at the end of the pulse. Thus the invalid
states can be eliminated.

The circuit diagram and truth table is shown below.

55
2. D Flip Flop

D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the
figure you can see that the D input is connected to the S input and the complement of the D input
is connected to the R input. The D input is passed on to the flip flop when the value of CP is ’1′.
When CP is HIGH, the flip flop moves to the SET state. If it is ’0′, the flip flop switches to the
CLEAR state.

The circuit diagram and truth table is given below.

56
3. J-K Flip Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.The behavior
of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J stands for SET
and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.The
circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a
feedback to the input of the AND along with other inputs like K and clock pulse [CP]. So, if the
value of CP is ’1′, the flip flop gets a CLEAR signal and with the condition that the value of Q
was earlier 1. Similarly output Q’ of the flip flop is given as a feedback to the input of the AND

57
along with other inputs like J and clock pulse [CP]. So the output becomes SET when the value
of CP is 1 only if the value of Q’ was earlier 1.

The output may be repeated in transitions once they have been complimented for J=K=1 because
of the feedback connection in the JK flip-flop. This can be avoided by setting a time duration
lesser than the propagation delay through the flip-flop. The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered construction.

The circuit diagram and truth-table of a J-K flip flop is shown below.

58
Pin Diagrams of Basic gates ICs used in experiment:
 7474 Dual D-flip flop with preset and clear

 7476 Dual JK-flip flop with preset and clear

RESULT:Using the ICs of logic gates we can study and verify the different flip flops like D, JK and
RS.

PRECAUTIONS: All the connections should be made properly.

59
 EXPERIMENT NO-9

AIM: Construct a divide by 2,4 & 8 asynchronous counter. Construct a 4-bit binary
counter and ring counter for a particular output pattern using D flip flop.

APPARATUS /COMPONENTS REQUIRED:

Breadboard, Digital IC 7474,Connecting wires,Multimeter,CRO,Clock Pulse generator.

THEORY: A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down counter is one
that is capable of progressing in increasing order or decreasing order through a certain sequence.
An up/down counter is also called bidirectional counter. Usually up/down operation of the
counter is controlled by up/down signal. When this signal is high counter goes through up
sequence and when up/down signal is low counter follows reverse sequence.

Asynchronous or ripple counters are arranged in such a way that the output of one flip flop
changes the state of the next. In a long chain of ripple counter stages, the last flip flop changes
its state considerably later than the first FF due to propagation delays in each stage. Problems
occur if this delay is longer than the response time of other logic elements connected to the
circuit. An even more serious source of error results because the outputs of a ripple counter
during changes of state often correspond to intermediate states outside of the intended sequence.
If the output lines are connected to logic which can respond to these in-between states, glitches
can occur that are so fast the error may be difficult to track down.

The 2-bit ripple counter circuit has four different states, each one corresponding to a count value.
Similarly, a counter with n flip-flops can have 2 to the power n states. The number of states in a
counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.

A mod-n counter may also described as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for
every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter.

Divide by Two Counter

The edge-triggered D-type ip-ops which we introduced in the previous Section are quite useful
and versatile building blocks of sequential logic. A simple application is the divide-by-2counter
shown in Fig. 1, along with the corresponding timing diagram.

60
Divide by four Counter

Since the Q output of the first flip flop changes every time the clock input goes low, it effectively
divides the input frequency by 2. The other output of the flip flop becomes the clock input to the

61
next stage, so the output of the second flip flop divides the original input frequency by 4. Hence
the term "divide-by-4" or "modulo-4".

Divide by Eight Counter

We can chain as many ripple counters together as we like. A three bit ripple counter will count
23=8 numbers, and an n-bit ripple counter will count 2n numbers.

The problem with ripple counters is that each new stage put on the counter adds a delay. This
propagation delay is seen when we look at a less idealized timing diagram:

Ring Counter
A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last
flip flop connected to the input of the first. It is initialised such that only one of the flip flop
output is 1 while the remander is 0. The 1 bit is circulated so the state repeats every n clock

62
cycles if n flip-flops are used. The "MOD" or "MODULUS" of a counter is the number of unique
states. The MOD of the n flip flop ring counter is n.
The following is a 4-bit ring counter constructed from D flip-flops. The output of each stage is
shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all
the flip-flops except the first one FF0 are reset to 0. FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter.
Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of
state usage. But the major advantage of a ring counter over a binary counter is that it is self-
decoding. No extra decoding circuit is needed to determine what state the counter is in.

IC used for realizing above counters:

63
RESULT: By using 7474 IC we can verify the truth table for different counters.

CONCLUSION: Thus the 4 bit ripple counter mod 10/ mod 12 ripple counters was implemented
and the truth table was verified.
PRECAUTIONS:

1. All IC s should be check ed before starting the experiment .

2. All the connection should be tight.
3. Always connect ground first and then connect Vcc .
4. Suitable typ e wi re should be used for different types of circuit.
5. The kit should be off before change the connections .
6. After completed the experiments switch off the supply of the apparatus.

64
 EXPERIMENT NO-10

AIM: Perform input/output operations on parallel in/parallel out and serial in/ serial out
register using clock.

APPARATUS REQUIRED: Trainer kit, Digital I.C.7495, Connecting wires

THEORY:

A flip-flop stores 1-bit of digital information. It is also referred to as 1-bit register. An array of
flip-flops is required to store the no. of bits. This is called register. The data can be entered into
or retrieved from the register. A register is capable of shifting its binary information in one or
both directions is known as shift register. The logical configuration of shift register consist of a
D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip
flops receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.So depending on the way how the data can be entered or
retrieved there are four possible modes of operation.

1) Serial in serial out (SISO)

2) Serial in parallel out (SIPO)

3) Parallel in serial out (PISO)

4) Parallel in parallel out (PIPO)

Serial in serial out (SISO)

A Serial-in Serial-out shift register can be implemented using D-type flip-flops joined
together, the output of one flip-flop used as the input to the next flip-flop. The circuit
for a 4-bit Serial-in Serial-out shift register is shown below.

The operation of the serial-in Serial-out shift register can be easily explained.
Consider the circuit shown. On each clock edge (rising in this case) we can say the
65
following about the outputs of each stage of the register (i.e. each D-type flip-flop in
the register):

Waveforms

Serial in parallel out (SIPO)

In such types of operations, the data is entered serially and taken out in parallel fashion.

 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.

66
 As soon as the data loading gets completed, all the flip-flops contain their required data, the
outputs are enabled so that all the loaded data is made available over all the output lines at the
same time.

 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO
mode is same as that of SISO mode.

Truth Table

Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0

Parallel-in to Serial-out (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format i.e. all the data bits enter their
inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out
sequentially in the normal shift-right mode from the register at Q representing the data present at
PA to PD. This data is outputted one bit at a time on each clock cycle in a serial format. It is

67
important to note that with this system a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.

Truth Table

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

As this type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which
can be sent directly to a computer or transmitted over a communications line.

Parallel-in to Parallel-out (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register
also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input pins PA to PD
and then transferred together directly to their respective output pins QA to QA by the same clock
pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading
and unloading is shown below.

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TRUTH TABLE:

CLK DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

Pin Diagram for IC 7495:

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70
RESULT: Thus the Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in
parallel out shift registers were implemented using IC 7495.

CONCLUSION: shift registers using IC 7495 in all its modes i.e.SIPO/SISO, PISO/PIPO are
verified and outputs are successfully observed on CRO.
PRECAUTIONS:
1. All the connections should be made properly.
2. IC should not be reversed
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