Eece 320 Digital Systems Design: Chapter 6 Combina9onal Logic Design Prac9ces

EECE
320
Digital Systems Design

Chapter 6

Combina9onal Logic Design Prac9ces

EECE320: Combinational Practices © Ali Chehab 1

Combina9onal Logic Design Prac9ces
§  Prac%cal systems require dozens of inputs and outputs
•  Too large to solve by direct theore%cal techniques
§  Solu%on: Structured design approach
•  Decompose system into smaller subsystems that are simpler to design
§  We consider several ‘useful’ structures used to design
subsystems
•  Decoders/encoders
•  Mul%plexers/Demul%plexers
•  Comparators
•  Adders/Subtractors/Mul%pliers/ALUs
§  Other universal building blocks
•  Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs)
§  ICs that have their func%on “programmed” into them aKer they
are manufactured.
PLD
PLA PAL CPLD FPGA

(Programmable (Programmable (Complex PLD) (Field Prog.
Logic Array) Array Logic) Gate Array)
• 2-level structure of • Enhanced PLAs • For large designs • Has a much larger # of
AND-OR gates with reduced costs • Collection of logic blocks
with programmable multiple PLDs with • Larger interconnection
connections an interconnection network
structure • Largest manufacturer:
Xilinx

Combina9onal PLDs
§  Programmable Logic Arrays (PLAs)
•  A PLA is a combina%onal, 2-‐level AND-‐OR device that can be
programmed to realize a SOP expression.
•  An (NxM) PLA with P products has the following limita%ons:
§  N = number of inputs
§  M = number of outputs
§  P = number of product terms << 2N
§  The number of AND gates = P (2N-‐input each)
§  The number of OR gates = M (p-‐input each)
•  Connec%ons from inputs to AND gates are programmed according to
the desired product terms.
•  Connec%ons from outputs of AND gates to OR gates are programmed
according to the desired SOP expression.

Example: A 4x3 PLA with 6 Product Terms
§  Six 8-input AND gates, Three 6-input OR gates
§  The device is programmed by keeping the needed connections!
programmable
connections
inputs outputs

4x3 PLA with 6 Product Terms -‐ Compact
§  It can implement 3 functions of 4-variable each, with 6
or less total number of products

Example: 4x3 PLA with 6 Product Terms
§  O1 = I1.I2 + I1’.I2’.I3’.I4’ §  O2 = I1.I3’ + I1’.I3.I4 + I2
§  O3 = I1.I2 + I1.I3’ + I1’.I2’.I4’
4x3 PLA with 6 Product Terms -‐ Constants
§  To produce constant outputs of 1 or 0 we can do:
§  No connection to inputs of AND è 1

§  No connection to inputs of OR è 0
Programmable Array Logic Devices (PALs)
§  A PAL is a special case of a PLA
•  OR array is fixed
•  AND array programmable
•  Bidirec%onal input/output pins

§  EX: PAL16L8 has
•  64 rows and 32 columns programmable AND array (2048 fuses)
•  64 AND gates each with 32 inputs
•  AND gate outputs cannot be shared
•  Each output has a 3-‐state output variable signal and inverted. The
output can be used as an input in a first pass for a func%on with more
than 7 terms

PAL16L8

PAL16L8 – Cont’d

PAL16L8 – Logic Symbol
§  10 Input pins, 8 Input/Output pins + 1 Power pin

and 1 GND pin: 20-pin package

Generic Array Logic Devices (GALs)
§  GAL16V8 can be configured to emulate the AND-‐OR, flip-‐flop,
and output structure of any of a variety of combina%onal and
sequen%al PAL devices.
§  It can be electrically erased and reprogrammed
§  It has an XOR at the output with 1 input connected to ground
via a fuse.
•  When the fuse is intact, it passes the output
•  When the fuse is blown, the input is high and inverts the output
§  The following figure shows the GAL16V8 configured as a
combina%onal device similar to the PAL16V8
GAL16V8
Decoders
§  A decoder is a mul%ple-‐input, mul%ple-‐output logic circuit that converts
coded inputs into coded outputs.
§  In general, the input and output codes are different, and the output code
has more bits than the input code.
§  There is a one-‐to-‐one mapping from input codewords to output codewords.
§  The most commonly used output code is the 1-‐out-‐of-‐m code where 1 bit is
asserted at a %me.
•  Ex: m=4, the 1-‐out-‐of-‐4 code has the codewords:
0001, 0010, 0100, 1000 (ac9ve high)
•  For ac9ve low, the codewords are
1110, 1101, 1011, 0111
§  The n-‐bit code is typically used for the input
•  EX: n=3, the 8 codewords are:
000, 001, …, 111
Binary Decoders (n-‐to-‐2n decoders)
§  The input is an n-‐bit binary code and the
output is a 1 out-‐of-‐2n code.
§  It is not necessary to use all outputs of a
decoder or to decode all possible input
combina%ons.
74x139 Dual 2-‐to-‐4 Decoder (MSI Part)
74x138 3-‐to-‐8 Decoder
74x138 3-‐to-‐8 Decoder
Cascading Binary Decoders
§  Multiple binary decoders can be
used to decode larger code
words.
§  EX: using two 3-to-8 decoders
to construct a 4-to-16 decoder.
§  When EN_L = 1, the decoder is
inactive.
§  When EN_L = 0, the MSB bit N3
is used to select between the
upper and lower decoders.
•  N3 = 0, select upper decoder
•  N3 = 1, select lower decoder
•  N2,N1,N0 select appropriate
output within each decoder.
2-‐to-‐4 Decoder in VHDL -‐ Behavioral
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder2to4 IS
Port ( DATA: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;
Y : OUT STD_LOGIC_VECTOR (0 TO 3) ) ;
END decoder2to4 ;
ARCHITECTURE behave OF decoder2to4 IS
BEGIN
PROCESS (DATA)
BEGIN
CASE DATA IS
WHEN “00” => Y <= “1000” ;
WHEN “01” => Y <= “0100” ;
WHEN “10” => Y <= “0010” ;
WHEN “11” => Y <= “0001” ;
WHEN OTHERS => Y <= “0000” ;
END CASE ;
END PROCESS;
END behave;
LIBRARY IEEE;
ENTITY V3to8dec IS
Port ( G1, G2, G3 : IN STD_LOGIC ;
A : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
Y : OUT STD_LOGIC_VECTOR(0 TO 7) ) ;
END V3to8dec ;
ARCHITECTURE V3to8dec _b OF V3to8dec IS
SIGNAL Y_s : STD_LOGIC_VECTOR(0 TO 7) ;
BEGIN
PROCESS(A, G1, G2, G3)
BEGIN
CASE A IS
WHEN “000” => Y_s <= “10000000” ;
WHEN “001” => Y_s <= “01000000” ;
WHEN “010” => Y_s <= “00100000” ;
WHEN “011” => Y_s <= “00010000” ;
WHEN “100” => Y_s <= “00001000” ;
WHEN“101” => Y_s <= “00000100” ;
WHEN “110” => Y_s <= “00000010” ;
WHEN “111” => Y_s <= “00000001” ;
WHEN OTHERS => Y_s <= “00000000” ;
END CASE ;
IF (G1 AND G2 AND G3) = ‘1’ THEN Y <= Y_s ;
ELSE Y <= “00000000” ;
END IF ;
END PROCESS;
END V3to8dec _b;
3-‐to-‐8 Decoder in VHDL – Data Flow
ARCHITECTURE V3to8dec_a OF V3to8dec IS
SIGNAL Y_s : STD_LOGIC_VECTOR(0 TO 7) ;

BEGIN
WITH A SELECT Y_s <=
“10000000” WHEN “000” ,
“01000000” WHEN “001” ,
“00100000” WHEN “010” ,
“00010000” WHEN “011” ,
“00001000” WHEN “100” ,
“00000100” WHEN “101” ,
“00000010” WHEN “110” ,
“00000001” WHEN “111” ,
“00000000” WHEN OTHERS;
Y <= Y_s WHEN (G1 AND G2 AND G3) = ‘1’ ELSE “00000000”;
END V3to8dec _a;
Encoders
§  The output code has fewer bits than the input code
§  The simplest encoder is the binary encoder (2n-‐to-‐n)
§  The input is a 1-‐out-‐of-‐2n code and the output is an n-‐bit
binary code
8-‐to-‐3 Encoder -‐ Example
§  Y0 = I1 + I3 + I5 + I7
§  Y1 = I2 + I3 + I6 + I7
§  Y2 = I4 + I5 + I6 + I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Priority Encoders
§  If mul%ple inputs are asserted simultaneously, the binary
encoder gives undesirable results
•  It is bemer to assign priori%es to input lines
•  Highest priority line is serviced first
•  EX: 8-‐to-‐3 Priority Encoder with IDLE output
§  If no input is asserted, IDLE is asserted
I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE
1 x x x x x x x 1 1 1 0
0 1 x x x x x x 1 1 0 0
0 0 1 x x x x x 1 0 1 0
0 0 0 1 x x x x 1 0 0 0
0 0 0 0 1 x x x 0 1 1 0
0 0 0 0 0 1 x x 0 1 0 0
0 0 0 0 0 0 1 x 0 0 1 0
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1
8-‐to-‐3 Priority Encoder
§  Intermediate Variables
§  H7 = I7 n H6 = I6.I7‘
§  H5 = I5.I6’.I7’ n H4 = I4.I7’.I6’.I5’
§  H3 = I3. I7’.I6’.I5’.I4‘ n H2 = I2. I7’.I6’.I5’.I4’.I3’
§  H1 = I1. I7’.I6’.I5’.I4’.I3’.I2’ n H0 = I0. I7’.I6’.I5’.I4’.I3’.I2’.I1‘
§  I7’.I6’.I5’.I4’.I3’.I2’.I1’
§  Output Equa%ons

§  A2 = H4 + H5 + H6 + H7
§  A1 = H2 + H3 + H6 + H7
§  A0 = H1 + H3 + H5 + H7
§  IDLE = (I0 + I1 + … + I7)’ = I0’.I1’. … .I7’
74x148 Priority Encoder
§  Inputs
and Outputs are active low
§  GS asserted if EI asserted and 1 or more Inputs are asserted
§  EO asserted if EI is asserted but no input is asserted, could
be connected to another EI (lower priority)
32-‐to-‐5 Priority Encoder – 4 (74x148)
§  GS signals are used as a
MSB
11 4-to-2 encoder to set the
11000 values of RA4 and RA3
11111
RA3 = GS1 + GS3
RA4 = GS2 + GS3
MSB
10 §  RGS is asserted if
10000
10111 any GS is asserted
§  The outputs A2-A0 of at
most one 74x148 will
MSB
01 be enabled at any time.
01000 They can be ORed to
01111 produce RA2-RA0
MSB
00
00000
00111
VHDL 8-‐to-‐3 Priority Encoder
library IEEE;
use IEEE.std_logic_1164.all;
en%ty encoder8to3 is
port (
I: in STD_LOGIC_VECTOR (7 downto 0);
A: out STD_LOGIC_VECTOR (2 downto 0)
);
end encoder8to3;
architecture encoder8to3 of encoder8to3 is
func%on CONV_STD_LOGIC_VECTOR(arg: integer; size: integer)
return std_logic_vector is
variable result : std_logic_vector(size-‐1 downto 0);
variable temp : integer;
begin
temp := arg;
for i in 0 to size-‐1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
temp := temp/2;
end loop;
return result;
end;
begin
process (I)
variable j: integer range 7 downto 0;
begin
for j in 7 downto 0 loop
if I(j) = '1' then
A <= CONV_STD_LOGIC_VECTOR(j, 3);
exit;
end if;
end loop;
end process;
end encoder8to3;
Three-‐State Devices
§  Three-‐state buffers
EN
§  If Enable line is asserted, the device acts like a normal

buffer or inverter
§  If Enable is negated, the output “floats”: High
Impedance (HI-Z) or in disconnected state
§  They allow multiple sources to share a single party line
as long as 1 device talks on the line at one time.
Three-‐State Devices
74x541: 8 3-‐State Buffer Chip
Using a 74x541 as a Microprocessor Input Port
read operation
8-bit bus
74x245: Bus Transceiver Enabling 2-‐Way Communica9on
§  A bus transceiver

contains pairs of 3-state
buffers connected in
opposite directions so
that data can be
transferred in either
direction.
§  A-to-B transfer: Dir = 1
§  B-to-A transfer: Dir = 0
Bidirec9onal Buses and Transceiver Opera9on
Mul9plexers
§  A mul%plexer is a digital switch: It connects data from 1 of n
sources to the output.
•  Cameras à Director à Screen
•  Registers à ALU
•  EX: 4-‐to-‐1 Mul%plexer
D0
S1 S0 Z
D1
Z 0 0 D0
D2
0 1 D1
D3
1 0 D2
1 1 D3
S1 S0
Z = S1’.S0’.D0 + S1’.S0.D1 + S1.S0’.D2 + S1.S0.D3

Mul9plexers
74x151 8-‐Input, 1-‐Bit Mul9plexer
(A’.B’.C’.D0).EN_L’
(A.B’.C’.D1) .EN_L’
EN_L
D0
D1
D2
D3 Y
D4 Y_L
D5 (A.B.C.D7) .EN_L’
D6
D7
CB A
74x157 2-‐Input, 4-‐Bit Mul9plexer
G_L
A[3:0]
Y[3:0]
B[3:0]
S
Expanding Mul9plexers
§  32-Input Mux
§  5 select lines XA4 – XA0
§  XA2, XA1, XA0 common
§  XA3, XA4 à Decoder
XEN_L
D0
D1
D2
.
. XOUT
.
D29
D30
D31
XXXXX
AAAAA
4 3 2 1 0
Demul9plexers
§  The function of a Demux is the inverse of a Mux: It routes a single
source to 1 of n outputs depending on select lines values
§  A decoder with Enable input can be used as a demultiplexer

VHDL MUX : 4 Inputs, 8 Bits – Behavioral
LIBRARY IEEE;
ENTITY mux4in8b IS
Port ( S : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
A, B, C, D : IN STD_LOGIC_VECTOR( 1 TO 8) ;
END mux4in8b;
ARCHITECTURE mux4in8b _BV OF mux4in8b IS
BEGIN
PROCESS (S, A, B, C, D)
BEGIN
CASE S IS
WHEN “00” => Y <= A;
WHEN “01” => Y <= B;
WHEN “10” => Y <= C;
WHEN “11” => Y <= D;
WHEN OTHERS => Y <= (OTHERS => ‘U’); -‐-‐-‐-‐ Output is unknown
END CASE;
END PROCESS;
END mux4in8b _BV;
VHDL MUX : 4 Inputs, 8 Bits – Data Flow
LIBRARY IEEE;

ENTITY mux4in8b IS
Port ( S : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
A, B, C, D : IN STD_LOGIC_VECTOR( 1 TO 8) ;
END mux4in8b;

ARCHITECTURE mux4in8b _DF OF mux4in8b IS
BEGIN
WITH S SELECT Y <=
A WHEN “00” ;
B WHEN “01” ;
C WHEN “10” ;
D WHEN “11” ;
(OTHERS => ‘U’) WHEN OTHERS;

END mux4in8b _DF;
Specialized 4-‐Input, 18-‐Bit Mul9plexer
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL

En9ty mux4in18b is
Port( S: in std_logic_vector(2 downto 0); -‐-‐-‐-‐-‐-‐-‐ ABACADAB
A, B, C, D: in std_logic_vector(1 to 18);
Y: out std_logic_vector(1 to 18) );
End mux4in18b;
Specialized 4-‐Input, 18-‐Bit Mul9plexer
Architecture mux4in18b of mux4in18b is
Begin
Process (S, A, B, C, D)
begin
case S is
when “000” | “010” | “100” | “110” => Y <= A;
when “001” | “111” => Y <= B;
when “011” => Y <= C;
when “101” => Y <= D;
when others => Y <= (others => ‘U’)
end case;
end process;
End mux4in18b;
Exclusive-‐OR Gates and Parity Circuits
§  An XOR gate is a 2-‐input gate whose
output is 1 if exactly one of its inputs is
1. (or if the inputs are different)
§  An XNOR produces a 1 if its inputs are
the same.
§  X ⊕ Y = X’.Y + X. Y’
Exclusive-‐OR Gates and Parity Circuits
§  Any two signals (inputs or output) of an XOR or XNOR

gate may be complemented without changing the
resulting function.
§  EX: X’ ⊕ Y’ = X.Y’ + X’.Y = X ⊕ Y
§  An XOR gate detects the parity of its inputs:
•  Odd number of ones --> output = 1
•  Even number of ones --> output = 0
Parity Circuit Structures
Daisy Chain
Tree Structure
§  By inverting the output we get an even parity circuit

74x280 9-‐Bit Parity Generator
Behavioral VHDL Program: 9-‐Input Parity Checker
LIBRARY IEEE;

En9ty parity9 is
Port( I: in std_logic_vector(1 to 9);
EVEN, ODD: out std_logic );
End parity9;

Architecture parity9 of parity9 is
Begin
Behavioral VHDL Program: 9-‐Input Parity Checker
Process (I)
variable p: std_logic;
begin
p := I(1);
for j in 2 to 9 loop
if I(j) = ‘1’ then p:= not p; end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
End parity9;
Structural VHDL: Parity Checker
LIBRARY IEEE;

En9ty V74x280 is
Port( I: in std_logic_vector(1 to 9);
EVEN, ODD: out std_logic );
End V74x280;

Architecture V74x280 of V74x280 is
Component vxor3 port (A, B, C: in std_logic; Y: out std_logic);
End component;
Signal Y1, Y2, Y3, Y3N: std_logic;
Structural VHDL: Parity Checker
Begin
U1: vxor3 port map (I(1), I(2), I(3), Y1);
Y3N <= not Y3;
U4: vxor3 port map (Y1, Y2, Y3, ODD);
U5: vxor3 port map (Y1, Y2, Y3N, EVEN);
End V74x280;
Comparator Structure
§  A 1-‐bit XOR can be viewed as a 1-‐bit comparator
§  A combina%on of XORs followed by OR opera%on can be used
to design comparators with any number of inputs
Itera9ve Circuits
§  An itera%ve circuit is a special type of combina%onal circuit
that has the following structure:
§  The boundary inputs are usually connected to fixed logic
values
§  The boundary outputs provide important informa%on
Itera9ve Circuits
§  Itera%ve circuits are well suited to problems that can be
solved by a simple itera%ve algorithm:
1.  Set C0 to its ini%al value and and set i to 0
2.  Use Ci and PIi to determine the values of POi and Ci+1
3.  Increment i
4.  If i < n, go to step 2
§  The loop of steps (2 to 4) can be expanded by providing a
separate combina%onal circuit to perform step 2 for every i
An Itera9ve Comparator Circuit
§  Two N-‐bit values X and Y can be compared one bit at a %me
using a single bit EQi at each step to keep track of whether all
of the bit-‐pairs have been equal so far:
1.  Set EQ0 to 1 and set i to 0
2.  If EQi = 1 and Xi = Yi, set EQi+1 to 1. Else set it to 0.
3.  Increment i
4.  If i<n, go to step 2.
An Itera9ve Comparator Circuit

Eece 320 Digital Systems Design: Chapter 6 Combina9onal Logic Design Prac9ces

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Eece 320 Digital Systems Design: Chapter 6 Combina9onal Logic Design Prac9ces

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EECE

EECE320: Combinational Practices © Ali Chehab 1

EECE320: Combinational Practices © Ali Chehab 2

PLA PAL CPLD FPGA

EECE320: Combinational Practices © Ali Chehab 3

EECE320: Combinational Practices © Ali Chehab 4

EECE320: Combinational Practices © Ali Chehab 5

EECE320: Combinational Practices © Ali Chehab 6

§  No connection to inputs of AND è 1

EECE320: Combinational Practices © Ali Chehab 9

EECE320: Combinational Practices © Ali Chehab 10

EECE320: Combinational Practices © Ali Chehab 11

§  10 Input pins, 8 Input/Output pins + 1 Power pin

EECE320: Combinational Practices © Ali Chehab 12

§  Output Equa%ons

§  If Enable line is asserted, the device acts like a normal

§  A bus transceiver

Z = S1’.S0’.D0 + S1’.S0.D1 + S1.S0’.D2 + S1.S0.D3

§  A decoder with Enable input can be used as a demultiplexer

§  Any two signals (inputs or output) of an XOR or XNOR

§  By inverting the output we get an even parity circuit

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Eece 320 Digital Systems Design: Chapter 6 Combina9onal Logic Design Prac9ces

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Eece 320 Digital Systems Design: Chapter 6 Combina9onal Logic Design Prac9ces

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Copyright:

Available Formats

EECE

EECE320: Combinational Practices © Ali Chehab 1

EECE320: Combinational Practices © Ali Chehab 2

PLA PAL CPLD FPGA

EECE320: Combinational Practices © Ali Chehab 3

EECE320: Combinational Practices © Ali Chehab 4

EECE320: Combinational Practices © Ali Chehab 5

EECE320: Combinational Practices © Ali Chehab 6

§ No connection to inputs of AND è 1

EECE320: Combinational Practices © Ali Chehab 9

EECE320: Combinational Practices © Ali Chehab 10

EECE320: Combinational Practices © Ali Chehab 11

§ 10 Input pins, 8 Input/Output pins + 1 Power pin

EECE320: Combinational Practices © Ali Chehab 12

§ Output Equa%ons

§ If Enable line is asserted, the device acts like a normal

§ A bus transceiver

Z = S1’.S0’.D0 + S1’.S0.D1 + S1.S0’.D2 + S1.S0.D3

§ A decoder with Enable input can be used as a demultiplexer

§ Any two signals (inputs or output) of an XOR or XNOR

§ By inverting the output we get an even parity circuit

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§  No connection to inputs of AND è 1

§  10 Input pins, 8 Input/Output pins + 1 Power pin

§  Output Equa%ons

§  If Enable line is asserted, the device acts like a normal

§  A bus transceiver

§  A decoder with Enable input can be used as a demultiplexer

§  Any two signals (inputs or output) of an XOR or XNOR

§  By inverting the output we get an even parity circuit