 1st computer ,hard drive 5MB in  Laptop with 1TB hard-drive

1956 now a days

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 1st camera  Camera

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 Very Large Scale Integration ( Within IC).
 In 1965, Gordon E. Moore, the co-founder of Intel, made this
observation that became Moore's Law.
 Moore's Law states that the number of transistors on a
microchip doubles about every two years, though the cost of
computers is halved.
 Another tenet of Moore's Law says that the growth of
microprocessors is exponential.

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 SSI(Small Scale Integration ) : 10–100 transistors/chip or 3 - 30 gates
/chip(logic gates,flip flops)
 MSI(Medium Scale Integration ) :100–1000 transistors/chip or 30 -
300 gates /chip(counters,multiplexers,registers)
 LSI(Large Scale Integration ) : 1000–10,000 transistors/chip or 300 -
3000 gates /chip(8 bit processors)
 VLSI( Very Large Scale Integration ) :10,000–1,00,000 transistors/chip
or morethan 3000 gates /chip.(16 bit and 32 bit processors) (most
popular)
 ULSI( Ultra Large Scale Integration ) :10power 6 –10 power 7
transistors/chip(smart sensors,VR reality modules)
 GSI( Giant Scale Integration ) :greater than 10 power 7
transistors/chip

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10
 Specifications:- According to customer demand (Ex: mobile (low
power consumption, high speed, good camera quality, good video
quality, higher memory etc.).
 Architecture design:-

The architecture team will design an architecture ( block diagram

having memories, processor, other design, how they are connected
(using all details in the specification) .This architecture team will
estimate the block area, how much power is required and cost for the
design.

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 RTL design:-
Register transfer level(RTL) .The above architecture is converted
into HDL (Hardware Description Language) code. This code describes how
data is transformed as it is passed from register to register
 RTL verification:-

After the RTL design by applying test cases we verify the design in
verification stage (takes 60% of total time).If any mistakes are found then
the design is resend to the RTL designing department.

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 Synthesis:-
It is a process of converting the RTL code into gate level netlist(generating
hardware from code).Up to RTL verification the design is technology
independent. In synthesis process the design is converted into technology
dependent (what technology you are using for transistors)
1.Translation:- The RTL code is converted in to Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by SOP and
POS optimization method.
3.Mapping:- In this technology independent Boolean expression is
converted into technology dependent and generates the gate level net
list.

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 DFT:-
Design for testability(DFT) is a technique used to test after
production.
 Floorplan:-

It is the process of placing blocks/macros in the chip/core area

there by determining routing areas between them.
 Placement:-

Placement is the process of automatically assigning correct

position to standard cells on the chip with no overlapping.

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 CTS (clock tree synthesis):-
In the chip clock signal is essential to the flip flops, to give the
clock signal from clock source we built the clock tree. It is the process of
balancing the clock skew and minimizing insertion delay in order to meet
timing and power.
 Routing:-

In this stage we connect all the cells with the metal straps.
 Signoff:-

In signoff stage all the tests are done to check the quality and
performance of the layout before tape out.

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 Fabrication:-
By the GDS II file information we fabricate the chip. The total design
is converted into chip by the manufacturing process.

 Packaging and testing:-

After the fabrication process we test the chip. If there is any fault in
the design then we modifies the design by repeating the steps. If there are no
faults then chip will go to packaging.

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 VLSI industry deployed with two measures domain
 Front End Development
 In this field you have to cop with programming Languages respective to
Hardware Description Language HDL for Protocol Designing and complex
Digital designs.
 Digital design Engineer : Digital knowledge, Verilog HDL
 Verification engineer :Digital knowledge, verilog, system verilog , UVM
 Back End Development
 Physical Design Engineer :
 Works on digital design on CMOS level one must have sound knowledge of
semiconductor theory.
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 Easy to design.
 Storage is easy.
 Less influence of noise.
 Transmitted over long distance.
 can be programmable.
 High speed data transmission
 Ease of design.

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1. If something goes wrong which one is easy to analyse?
2. Which one have less no of components?
3. Which one will have less no of code lines?

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 You can specify digital systems much faster than drawing the complete
schematics.
 The debug cycle is also often much faster.
 Modifications require code changes instead of schematic rewiring.
 HDLs are used for both simulation and synthesis.

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 A hardware description language (HDL) is a programming
language used to describe the behaviour or structure of digital
circuits (ICs).
 HDLs are also used to stimulate the circuit and check its
response.
 VHDL and Verilog are officially endorsed IEEE ( Other HDLs
include JHDL (Java HDL), and proprietary HDLs such as Cypress
Semiconductor Corporation's Active-HDL).
 VHDL stands for “very high-speed integrated-circuit hardware
description language.”
 when you are writing HDL code, you should remember is that you
are describing real hardware, not writing a computer program.
 Example: let you have to design a circuit that checks whether a
number is even or not.
 Solution: number%2==0, number is even ( gives correct result ,what
about hardware synthesized??
 Another solution: number[0]==0,(hardware area is less then
previous number is even
 So you should think about the hardware you intend to produce.
 You have to check 3 things in your hardware ( minimum area,
minimum power consumption, minimum delay)
Following are the four different levels of abstraction which can be
described by four different coding styles of Verilog language:
• Behavioural or Algorithmic level (highest level) (procedural block)

• Dataflow level ( Boolean expression , operators are used)

• Gate level or Structural level ( either inbuilt modules or user

defines modules are used)
• Switch level (transistors are used , not synthesizable)
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 Simulators let you check the values of signals inside your system.

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 Synthesis converts the HDL code into digital logic circuits/ netlist /
hardware.

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Value Set
Verilog consists of only four basic values.
0 (logic zero, or false condition)
1 (logic one, or true condition)
x (unknown logic value)
z (high impedance state)
x and z have limited use for synthesis.

Wire
A wire represents a physical wire in a circuit and is used to connect
gates or modules. A wire does not store its value but must be driven
by a continuous assignment statement or by connecting it to the
output of a gate or module.
Reg
A reg (register) is a data object that holds its value from one
procedural assignment to the next. They are used only in
functions/tasks and procedural blocks. A reg is a Verilog variable
type and does not necessarily imply a physical register. In multi-bit
registers, data is stored as unsigned numbers and no sign extension
is done for what the user might have thought were two’s
complement numbers.
Input, Output, Inout:-

These keywords declare input, output and bidirectional ports of a

module or task.
Input and inout ports are of type wire.
An output port can be configured to be of type wire, reg,. The
default is wire.
A setup for applying test vectors to test a design.

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$display, $strobe, $monitor
• These commands have the same syntax, and display their values
as text on the screen during simulation.
• $display and $strobe display once every time they are executed,
whereas $monitor displays every time one of its parameters
changes.
• The difference between $display and $strobe is that $display
displays the parameters at the very start of the current
simulation time unit. $strobe displays the parameters at the very
end of the current simulation time unit.
• Format characters include %d (decimal), %h (hexadecimal), %b
(binary), %c (character), %s (string) and %t (time).
$random

$random generates a random integer (signed , 32 bit) every time it

is called. If the sequence is to be repeatable, the first time one
invokes random give it a numerical argument (a seed). Otherwise
the seed is derived from the computer clock.
$reset, $stop, $finish

$reset resets the simulation back to time 0; $stop halts the

simulator and puts it in the interactive mode where the user can
enter commands; $finish exits the simulator back to the operating
system.

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Behavioral Modeling

Verilog procedural statements are used to model a design at a higher

level of abstraction than the other levels.
They provide powerful ways of doing complex designs. However small
changes n coding methods can cause large changes in the hardware
generated.
Procedural statements can only be used in procedures.
Procedural Assignments

Procedural assignments are assignment statements used within Verilog

procedures (always and initial blocks).
Only reg variables and integers (and their bit/part-selects and
concatenations) can be placed left of the procedural assignmnets
Blocking Assignments
Procedural (blocking) assignments (=) are done sequentially in the
order the statements are written. A second assignment is not
started until the preceding one is complete.
Nonblocking Assignments
Procedural (nonblocking) assignments (<=), which follow each
other in the code, are done in parallel. The right hand side of
nonblocking assignments is evaluated starting from the completion
of the last blocking assignment or if none, the start of the
procedure. The transfer to the left hand side is made according to
the delays.
For synthesis
• One must not mix “<=” or “=” in the same procedure.
• “<=” used for sequential design while “=” is used for
combinational design