2021

NANAOMATERIAL LAB
RECORD
DEEKSHITH KUMAR

20ETEC12004

2020-2022

M.TECH VLSI AND NANOTECHNOLOGY

RAMAIAH UNIVERSITY OF APPLIED SCIENCES, BANGALORE

Experiment No.1

NAND gate

1. Aim:

To design and simulate NAND gate in LTspice software

2. Theory:
The Logic NAND Gate is a combination of a digital logic AND gate and a NOT gate connected
together in series
̅̅̅̅̅̅̅
Output expression of OR gate Y=𝐴 ∗𝐵
A B ̅̅̅̅̅̅̅
Y=𝐴 ∗𝐵
0 0 1
0 1 1
1 0 1
1 1 0

3. Circuit:

Circuit of NAND gate

4. Plot/Result:

Waveform of logic NAND gate.

5. Conclusion and Inference:

Logic NAND gate has been designed and simulated using LTspice with RIT models.
Experiment No.2

OR gate and to find propagation delay

1. Aim:

To design and simulate OR gate in LTspice software and to find propagation delay of the
circuit.

2. Theory:
The Logic OR Gate is a type of digital logic circuit whose output goes HIGH to a logic
level 1 only when one or more of its inputs are HIGH
Output expression of OR gate Y=A+B
A B Y=A+ B
0 0 0
0 1 1
1 0 1
1 1 1

3. Circuit:

4. Plot/Result:
Waveform of logic OR gate.

The propagation delay obtained is 5.77ms.

5. Conclusion and Inference:

Logic OR gate has been designed and simulated using LTspice with RIT models.
Propagation delay has also been obtained.
Experiment No.3

AND gate and to find leakage power

1. Aim:

To design and simulate AND gate in LTspice software and to find leakage power of the
circuit.

2. Theory:
The Logic AND Gate is a type of digital logic circuit whose output goes HIGH to a
logic level 1 only when all of its inputs are HIGH
Output expression of AND gate Y=A*B
A B Y=A* B
0 0 0
0 1 0
1 0 0
1 1 1

3. Circuit:

Circuit of AND gate

4. Plot/Result:
Waveform of AND gate

The obtained current when all the input voltages are zero is 5.099pA.

Leakage power P=V*I

P=5*5.099p= 25.04pW

The obtained leakage power is 25.04pW.

5. Conclusion and Inference:

Logic AND gate has been designed and simulated using LTspice with RIT models. Leakage
power has been calculated by finding current at the load.
Experiment No.4

NOR gate and to find leakage power

1. Aim:

To design and simulate NOR gate in LTspice software and to find leakage power of the
circuit.

2. Theory:
The Logic NOR Gate gate is a combination of the digital logic OR gate and an inverter or
NOT gate connected together in series
Output expression of AND gate Y= ̅̅̅̅̅̅̅̅
𝐴+𝐵
A B Y= ̅̅̅̅̅̅̅̅
𝐴+𝐵
0 0 1
0 1 0
1 0 0
1 1 0

3. Circuit:

Circuit of NOR gate

4. Plot/Result:
Waveform of NOR gate

The obtained current when all the input voltages are zero is -0.00025fA.

Leakage power P=V*I

P=5*-0.00025f= -0.00125fW

The obtained leakage power is -0.00125fW.

5. Conclusion and Inference:

Logic NOR gate has been designed and simulated using LTspice with RIT models. Leakage
power has been calculated by finding current at the load.
Experiment No.5

3 Stage Ring Oscillator

1. Aim:

To design and simulate 3 stage ring oscillator in LTspice software .

2. Theory:
The ring oscillator is “an odd number of inverters are connected in a series form with
positive feedback & output oscillates between two voltage levels either 1 or zero to measure
the speed of the process. If this oscillator has 3 inverters then it is called a three-stage ring
oscillator.

3. Circuit:

Circuit of 3 stage Ring Oscillator

4. Plot/Result:
Waveform of 3 stage Ring Oscillator

5. Conclusion and Inference:

3 stage ring oscillator has been designed and simulated using LTspice with RIT models.