University of Baltistan Skardu

Submitted To: Sir Sadaqat Hussain

Submitted By: Mohsin Ejaz

Registration No: S23BSCS077

Semester : 2nd

Course: Digital Logic and Design

Department: Computer Science

Section: A

Session: (2023- 2027)

Lab Manual

Date: 10-12-2023
 THE EXPERIMENTS OF DIGITAL LOGIC
AND DESIGN CIRCUITS

LAB MANUAL

CONTENTS
1. Fundamental Logic Gate – AND, OR, NOT
2. Fundamental Logic Gate – NAND, NOR, XOR
3. Exclusive OR and Exclusive NOR Using Basic Logic Gate
4. Half Adder
5. Full Adder
6. De Morgan’s Law (I) and De Morgan’s Law (II)
7. Multiplexer
8. Demultiplexer
9. Latches
10. SR Flipflop
11. JK Flipflop
12. D and T Flipflop
Experiment 1 06-09-
2023
Fundamental Logic Gate – AND, OR, NOT

Purpose:

To show the input and output relationships of 2-input AND, OR, and 1-input NOT gates by
constructing their truth tables.

Circuit Diagram:

Procedure:

Step 1: In AND gate if the one input is low means “0” then the output is always low means
“0”.

Step 2: In OR gate if the one input is high means “1” then the output is always high means
“1”.

Step 2: In NOT gate the output is always the complement of given input.
Truth table:

If all of your procedures are connect, your results will be like this. If not, recheck your circuit
and repeat this experiment, then determine the problem.

Experiement 2 13-09-
2023
Fundamental Logic Gate – nand, nor, xor
Purpose:

To demonstrate the input and output relationships of 2-input NAND, NOR, AND XOR gates
by constructing their tables.

Circuit Diagram:
Procedure:

Step 1: In NAND gate if the one input is low means “0” then the output is always high
means “1”.

Step 2: In NOR gate if the one input is high means “1” then the output is always low means
“0”.

Step 3: In XOR gate if the inputs are different then the output is always high means “1”. And
if the inputs are same then the output is always low means “0”.

Truth table:

If you have wired everything correctly, the output of the three gates should be as follows:
Experiment 3 20-09-
2023
Exclusive OR Using Basic Logic Gate
Purpose:

1. To understand the logic function of Exclusive OR.

2. To verify the truth table of Exclusive OR.

3. To exercise how to combine Exclusive OR using the basic logic gate.

Circuit Diagram:

Truth table:
 Exclusive NOR Using Basic Logic Gate

Purpose:

1. For understanding the logic function of Exclusive NOR.

2. This experiment is to demonstrate the input and output relationships of XNOR gate by
constructing their associated truth table.

3. From this experiment you can exercise how to design the XNOR using the basic logic
gate.

Circuit Diagram:

Truth Table:

A B Y
 0 0 1

0 1 0

1 0 0

1 1 1

Experiment 4 27-09-
2023
Half Adder
A half adder is a digital logic circuit that performs binary addition of two single-bit binary
numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output
is the least significant bit (LSB) of the result, while the CARRY output is the most
significant bit (MSB) of the result, indicating whether there was a carry-over from the
addition of the two inputs. The half adder can be implemented using basic gates such as
XOR and AND gates.

Circuit Diagram:

Truth Table:
Experiment 5 28-09-
2023
Full Adder
Full Adder is the adder that adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. The C-OUT
is also known as the majority 1’s detector, whose output goes high when more than one
input is high.

Circuit Diagram:

Truth Table:
Experiment 6 11-10-
2023
De Morgan’s Law (I)

Purpose:

One of De Morgan’s Law is AB = A+B. This means that the NAND gate function is identical
to the OR gate function with complement input of A and B. From this experiment, you can
understand how to exchange gates for other gates, and verify that AB is exactly identical to
A+B.

Circuit Diagram:

Truth table:
The output results of these two circuits will have the identical results. The truth table likes as
follows

De Morgan’s Law (II)

Purpose:

Another of De Morgan’s Laws is that A+B = AB. This means that the NOR gate function is
equal to the AND gate function with complement input of A and B. After finished the
experiment you will learn about how to apply the De Morgan’s Law to your circuit design.

Circuit Diagram:
Truth table:

Experiment 7 18-10-
2023

Multiplexer (4x1 Mux)

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output
Y.One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines.

Circuit Diagram:

Diagram

One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines.

Truth table of 4x1 Multiplexer

Selection Lines Output

S1 S0 Y
 0 0 I0
0 1 I1
1 0 I2
1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as .
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

Experiment 8 25-10-
2023

De-Multiplexer (1x4 Mux)

1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2,
Y1 &Y0.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values
of selection lines s1 & s0.

Circuit Diagram:

Diagram
The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values
of selection lines s1 & s0.

The Truth table of 1x4 De-Multiplexer

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as

Y3=s1s0I
Y2=s1s0′I
Y1=s1′s0I
Y0=s1′s0′I
Experiment 9 01-11-
2023

Latches
SR Latch using NAND Gate
When using static gates as building blocks, the most fundamental latch is the simple SR latch,
where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR
or NAND logic gates. The stored bit is present on the output marked Q.

The circuit shown below is a basic NAND latch. The inputs are generally designated S and R
for Set and Reset respectively.

Circuit Diagram:

Truth table:
Experiment 10 08-11-
2023

SR Flipflop using NAND Gate

It is a Flip Flop with two inputs, one is S and other is R. S here stands for Set and R here
stands for Reset. Set basically indicates set the flip flop which means output 1 and reset
indicates resetting the flip flop which means output 0. Here clock pulse is supplied to operate
this flop flop, hence it is clocked flip flop.

Circuit Diagram:

Truth Table:
Experiment 11 15-11-
2023

JK Flipflop using NAND Gate

One of the most useful and versatile flip flop is the JK flip flop the unique features of a JK
flip flop are:

If the J and K input are both at 1 and the clock pulse is applied, then the output will change
state, regardless of its previous condition.

If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the
output. There is no indeterminate condition, in the operation of JK flip flop i.e. it has no
ambiguous state. The circuit diagram for a JK flip flop is shown in Figure :

Circuit Diagram:
Truth Table:

Experiment 12 16-11-
2023

D Flipflop using NAND Gate

D Flip flops or data flip flops or delay flip flops can be designed using SR flip flops by
connecting a not gate in between S and R inputs and tying them together. D flip flops can be
used in place of SR flip flops where you need only SET and RESET state.
Circuit Diagram:

Truth Table:

T Flipflop using NAND Gate

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-
flop work as a Toggle switch. The next output state is changed with the complement of the
present state output. This process is known as "Toggling"'.

Circuit Diagram:
Truth Table: