Digital circuits

Digital circuits are collections of devices that perform logical operations on two logical states,
represented by voltage levels. Standard operations such as AND, OR, INVERT,
EQUIVALENT, etc. are performed by devices known as gates. Groups of compatible gates can
be combined to make yes/no decisions based on the states of the inputs. For example, a simple
warning light circuit might check several switch settings and produce a single yes/no output.
More complicated circuits can be used to manipulate information in the form of decimal digits,
alphanumeric characters, or groups of yes/no inputs. These notes are intended to familiarize you
with the elementary principles of this field.

1.1 Combinational Logic Circuits

Combinational Logic Circuits are memoryless digital logic circuits whose output at any instant in
time depends only on the combination of its inputs.
The outputs of Combinational Logic Circuits are only determined by the logical function of their
current input state, logic “0” or logic “1”, at any given instant in time.

Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are
“combined” or connected together to produce more complicated switching circuits. These logic
gates are the building blocks of combinational logic circuits. An example of a combinational
circuit is a decoder, which converts the binary code data present at its input into a number of
different output lines, one at a time producing an equivalent decimal code at its output.
Combinational logic circuits can be very simple or very complicated and any combinational
circuit can be implemented with only NAND and NOR gates as these are classed as “universal”
gates.

Basic Gate
The basic building blocks of a computer are called logical gates or just gates. Gates are basic
circuits that have at least one (and usually more) input and exactly one output. Input and output
values are the logical values true and false. In computer architecture it is common to use 0 for
false and 1 for true. Gates have no memory. The value of the output depends only on the current
value of the inputs. A useful way of describing the relationship between the inputs of gates and
their output is the truth table. In a truth table, the value of each output is tabulated for every
possible combination of the input values. We usually consider three basic kinds of gates, and-
gates, or-gates, and not-gates (or inverters).
AND Gate
The AND gate implements the AND function. With the gate shown to the left, both inputs must
have logic 1 signals applied to them in order for the output to be a logic 1. With either input at
logic 0, the output will be held to logic 0.

Symbol Truth Table

There is no limit to the number of inputs that may be applied to an AND function, so there is no
functional limit to the number of inputs an AND gate may have. However, for practical reasons,
commercial AND gates are most commonly manufactured with 2, 3, or 4 inputs. A standard
Integrated Circuit (IC) package contains 14 or 16 pins, for practical size and handling. A
standard 14-pin package can contain four 2-input gates, three 3-input gates, or two 4-input gates,
and still have room for two pins for power supply connections.

OR Gate
The OR gate is sort of the reverse of the AND gate. The OR function, like its verbal counterpart,
allows the output to be true (logic 1) if any one or more of its inputs are true. Verbally, we might
say, "If it is raining OR if I turn on the sprinkler, the lawn will be wet." Note that the lawn will
still be wet if the sprinkler is on and it is also raining. This is correctly reflected by the basic OR
function. In symbols, the OR function is designated with a plus sign (+). In logical diagrams, the
symbol below designates the OR gate.

Symbol Truth Table

As with the AND function, the OR function can have any number of inputs. However, practical
commercial OR gates are mostly limited to 2, 3, and 4 inputs, as with AND gates.

NOT Gate or Inverter

The inverter is a little different from AND and OR gates in that it always has exactly one input as
well as one output. Whatever logical state is applied to the input, the opposite state will appear at
the output.

Symbol Truth Table

Combined gates
Sometimes, it is practical to combine functions of the basic gates into more complex gates, for
instance in order to save space in circuit diagrams. In this section, we show some such combined
gates together with their truth tables.
NAND-gate
The NAND-gate is an and-gate with an inverter on the output. So instead of drawing several
gates like this:

NOR-gate
The NOR-gate is an or-gate with an inverter on the output. So instead of drawing several gates
like this:

Exclusive-OR-gate/EX-OR
The exclusive-or-gate is similar to an OR gate. It can have an arbitrary number of inputs, and its
output value is 1 if and only if exactly one input is 1 (and thus the others 0). Otherwise, the
output is 0.

Exclusive-NOR-gate/EX-NOR
The exclusive-Nor-gate is similar to an N or-gate. It can have an arbitrary number of inputs, and
its output value is 1 if and only if the two input are of the same values (1 and 1 or 0 and 0).
Otherwise, the output is 0.

Multiplexer
Multiplexing is the property of combining one or more signals and transmitting on a single
channel.
The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational
circuit with more than one input line, one output line and more than one select line. It allows the
binary information from several input lines or sources and depending on the set of select lines,
particular input line, is routed onto a single output line.

2:1 MUX

In 2:1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line
S0, one of these 2 inputs will be connected to the output. The block diagram and the truth table of
the 2:1 multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4:1 MUX

Select Data Inputs Output

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

The truth table of a 4-to-1 multiplexer is shown above in which four input combinations 00, 10, 01 and 11
on the select lines respectively switches the inputs I0, I1, I2 and I3 to the output. That means when S1=0
and S0 =0, the output at Y is I0, similarly Y is D1 if the select inputs S1=0 and S0= 1 and so on.

Demultiplexer
The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the MUX ,
demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be bypassed to one
of its many output data lines.

The process of getting information from one input and transmitting the same over one of many outputs is
called demultiplexing. A demultiplexer is a combinational logic circuit that receives the information on a
single input and transmits the same information over one of 2n possible output lines.

Thus, a demultiplexer is a 1-to-N device where as the multiplexer is an N-to-1 device. The figure below
shows the block diagram of a 4:1 demultiplexer or simply a DEMUX.

It consists of 1 input line, 4 output lines and 2 select lines. In this, m selection lines are required to
produce 2m possible output lines

1:2 DEMUX
A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The signal
on the select line helps to switch the input to one of the two outputs. The figure below shows the
block diagram of a 1-to-2 demultiplexer with additional enable input.

In the figure below, there are only two possible ways to connect the input to output lines, thus
only one select signal is enough to do the demultiplexing operation. When the select input is
LOW, then the input will be passed to Y0 and if the select input is HIGH, then the input will be
passed to Y1.

The truth table of a 1-to-2 demultiplexer is shown below, in which the input is routed to Y0 and
Y1 depending on the value of select input S.

S D Y1

0 0 0

0 1 0

1 0 0

1 1 1
We can derive the Boolean Expressions for the outputs as follows:

Assume S is the Select Input, D is the Data Input and Y0 and Y1 are the outputs of the 1-to-2
Demultiplexer. From the above table, the output Y0 is active when the combination of select line
and input line are active low and high respectively, i.e., S=0, D=1.
Therefore, the expression for output Y0 is

Y0 = S*D

Similarly, the output Y1 is active when the combination of select line and input line are active
high, i.e., S=1, D=1.

Therefore, the expression for output Y1 is

Y1 = S*D

From the above truth table and the derived Boolean Expressions, the logic diagram of 1-to-2
demultiplexer can be designed using two AND gates and one NOT gate as shown in below
figure. When the select line S = 0, the first AND gate (A1) is enabled, while the second AND
gate (A2) is disabled.

Then, the data from the input flows to the output line Y0. Similarly, when S = 1, the second
AND gate (A2) is enabled and the first AND gate (A1) is disabled, thus data is passed to the Y1
output.

1:4 DEMUX
The truth table of this type of demultiplexer is given below. From the truth table it is clear that, when A=0
and B= 0, the data input is connected to output D0 and when A= 0 and B=1, then the data input is
connected to output Y1.

Comparators
The basic function of a comparator is to compare the magnitudes of two binary quantities to
determine the relationship of those quantities.
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B condition, one for A = B
condition and one for A < B condition.
A comparator used to compare two bits is called a single bit comparator. It consists of two inputs
each for two single bit numbers and three outputs to generate less than, equal to and greater than
between two binary numbers.
The figure below shows the block diagram of a single bit magnitude comparator. This
comparator compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G
(A>B).
The truth table for the single bit comparator is given below. When A B = 00 & 11, both inputs
are equal, therefore A=B output will be high. When AB = 01, B is more than A and hence A<B
is active. Similarly When AB = 10, A is more than B and hence A>B is active.

1.2 Sequential circuit

A sequential circuit is a logical circuit, where the output depends on the present value of the
input signal as well as the sequence of past inputs. While a combinational circuit is a function of
present input only. A sequential circuit is a combination of combinational circuit and a storage
element. The sequential circuits use current input variables and previous input variables which
are stored and provides the data to the circuit on the next clock cycle.

SR latch
An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and
relies only on the state of the S and R inputs. In the image we can see that an SR latch can be
created with two NOR gates that have a cross-feedback loop. SR latches can also be made from
NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called
an SR latch.
When a high is applied to the Set line of an SR latch, the Q output goes high (and Q1 low). The
feedback mechanism, however, means that the Q output will remain high, even when the S input
goes low again. This is how the latch serves as a memory device. Conversely, a high input on
the Reset line will drive the Q output low (and Q1 high), effectively resetting the latch's
"memory". When both inputs are low, the latch "latches" – it remains in its previously set or reset
state.
When both inputs are high at once, however, there is a problem: it is being told to simultaneously
produce a high Q and a low Q1. This produces a "race condition" within the circuit - whichever
flip flop succeeds in changing first will feedback to the other and asserts itself. Ideally, both
gates are identical and this is "metastable", and the device will be in an undefined state for an
indefinite period. The state of S = R = 1 is therefore "illegal" and should never be entered.

S R Q Q1

0 0 Latched

0 1 0 1

1 0 1 0

1 1 Metastable

When the device is powered up, a similar condition occurs, because both outputs, Q and Q1, are
low. Again, the device will quickly exit the metastable state due to differences between the two
gates, but it's impossible to predict which of Q and Q1 will end up high. To avoid spurious
actions, you should always set SR flip-flops to a known initial state before using them - you must
not assume that they will initialize to a low state.

SR Flop Flop:
The SR Flip-Flop is also known as the gated or clocked SR latch. The clocked SR latch or SR
flip-flop temporarily stores or holds the information until it is needed in digital circuits. 'S' and
'R' are the two inputs to the SR flip-flop. It has two outputs, the main output 'Q' and the
complements of the main output ' Q' '. The SR Flip-Flop is a storage element with only one bit.

The SR flip-flop is a gated SR flip-flop with a clock input circuitry that does not prevent the
illegal or invalid output state that can arise when both inputs S and R are equal to logic level "1".
The SR latch is constructed using two cross-coupled NAND gates. Let us discuss in detail about
these in the upcoming sections.
JK Flip-flop:

The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Due to its
versatility they are available as IC packages. The major applications of JK flip-flop are Shift
registers, storage registers, counters and control circuits. Inspite of the simple wiring of D type
flip-flop, JK flip-flop has a toggling nature. This has been an added advantage. Hence they are
mostly used in counters and PWM generation, etc. Here we are using NAND gates for
demonstrating the JK flip flop
Whenever the clock signal is LOW, the input is never going to affect the output state. The clock
has to be high for the inputs to get active. Thus, JK flip-flop is a controlled Bi-stable latch where
the clock signal is the control signal. Thus, the output has two stable states based on the inputs
which have been discussed below.
Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and QI. This
cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1”
state to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q1 through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and QI are always different we can use them to control
the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in
the following truth table.

The Truth Table for the JK Function

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit.
Also when both the J and the K inputs are at logic level “1” at the same time, and the clock input
is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-versa.
This results in the JK flip flop acting more like a T-type toggle flip-flop when both terminals are
“HIGH”.

T Flip-flop:

T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state
in SR flip – flop, we should provide only one input to the flip – flop called Trigger input or
Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the
next state output to complement of the present state output’.

We can design the T flip – flop by making simple modifications to the JK flip – flop. The T flip
– flop is a single input device and hence by connecting J and K inputs together and giving them
with single input called T, we can convert a JK flip – flop into T flip – flop. So a T flip – flop is
sometimes called as single input JK flip – flop.

The logic symbol of T flip – flop is shown below. It has one Toggle input (T) & one clock signal
input(CLK).
If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change
with the clock pulse because we know for JK Flip Flop J = K =0 output will be no change. On
the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock pulse, the Q output will
change to Q’ with the clock pulse because we know for JK Flip Flop J = K = 1 output will be
toggle. In other words, we may say that, if T = 1 and the device is clocked, and then the output
toggles its state.
The truth table shows that when T = 0, then Qn+1 = Qn, i.e., the next state is the same as the
present state and no change occurs. When T = 1, then Qn+1 = Q’n,i.e., the state of the flip-flop is
complemented.

D-type Flip-Flop Circuit

D flip – flops are also called as “Delay flip – flop” or “Data flip – flop”. They are used to store 1
– bit binary data. They are one of the widely used flip – flops in digital electronics. Apart from
being the basic memory element in digital systems, D flip – flops are also considered as Delay
line elements and Zero – Order Hold elements.

D flip – flop has two inputs , a clock (CLK) input and a data (D) input and two outputs; one is
main output represented by Q and the other is complement of Q represented by Q’. The symbol
of a D flip – flop is shown below.

A D flip – flop is constructed by modifying an SR flip – flop. The S input is given with D input
and the R input is given with inverted D input. Hence a D flip – flop is similar to SR flip – flop
in which the two inputs are complement to each other, so there will be no chance of any
intermediate state occurs. The major drawback of SR flip – flop is the race around condition
which in D flip – flop is eliminated (because of the inverted inputs). The circuit diagram of D
flip – flop is shown in below figure.

When we don’t apply any clock input to the D flip flop or during the falling edge of the clock
signal, there will be no change in the output. It will retain its previous value at the output Q. If
the clock signal is high (rising edge to be more precise) and if D input is high, then the output is
also high and if D input is low, then the output will become low. Hence the output Q follows the
input D in the presence of clock signal as shown in table below.

Truth Table for the D-type Flip Flop

Clk D Q Q Description

Memory
↓»0 X Q Q
no change

↑»1 0 0 1 Reset Q » 0

↑»1 1 1 0 Set Q » 1
Counter

Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also be designed with the help of flip flops.
Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following counters is driven by output of previous flip flops.
We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0,Q1,Q2,Q3
hence it is also called RIPPLE counter.

Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop.
 Synchronous counter circuit

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Binary 4-bit Synchronous Up Counter

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each
of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in
toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic
“1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal, advancing one state
for each pulse.
The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also
supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs
(Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but
without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same
time.
Then as there is no inherent propagation delay in synchronous counters, because all the counter
stages are triggered in parallel at the same time, the maximum operating frequency of this type of
frequency counter is much higher than that for a similar asynchronous counter circuit.
4-bit Synchronous Counter Waveform Timing Diagram

Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting
outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ). Therefore, this type of counter is also
known as a 4-bit Synchronous Up Counter.
However, we can easily construct a 4-bit Synchronous Down Counter by connecting
the AND gates to the Q output of the flip-flops as shown to produce a waveform timing diagram
the reverse of the above. Here the counter starts with all of its outputs HIGH ( 1111 ) and it
counts down on the application of each clock pulse to zero, ( 0000 ) before repeating again.

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and any number of flip-
flops can be connected or “cascaded” together to form a “divide-by-n” binary counter, the
modulo’s or “MOD” number still applies as it does for asynchronous counters so a Decade
counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.
All we need to increase the MOD count of an up or down synchronous counter is an additional
flip-flop and AND gate across it.

Shift Register
This sequential device loads the data present on its inputs and then moves or “shifts” it to its
output once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either the
left or the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore commonly
used inside calculators or computers to store data such as two binary numbers before they are
added together, or to convert the data from either a serial to parallel or parallel to serial format.
The individual data latches that make up a single shift register are all driven by a common clock
( Clk ) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:
▪ Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form.
▪ Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.
▪ Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
▪ Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:
Also, the directional movement of the data through a shift register can be either to the left, (left
shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting
within the same register thereby making it bidirectional. In this tutorial it is assumed that all the
data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs
still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned
LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output
of FFBand QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic
“1” has now moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so
on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic
level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.

Basic Data Movement Through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1
5 0 0 0 0

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the input
data to the register may consist of various combinations of logic “1” and “0”.
Serial-in to Serial-out (SISO) Shift Register
This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in
to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.
4-bit Serial-in to Serial-out Shift Register

You may think what’s the point of a SISO shift register if the output data is exactly the same as
the input data. Well this type of Shift Register also acts as a temporary storage device or it can
act as a time delay device for the data, with the amount of time delay being controlled by the
number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses.
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this type of data register a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which
can be sent directly to a computer or transmitted over a communications line. Commonly
available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output pins QA to QD by
the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for
parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

Truth Table
Clock PD PC PB PA QD QC QB QA
1 1 0 1 1 1 0 1 1

The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections between
the individual flip-flops since no serial shifting of the data is required.