Project Report

Course Title: Digital Logic Design

Course Code : CSE 345
Section: 2

Submitted to
Musharrat Khan
Senior Lecturer
Department of Computer Science & Engineering

Submitted by
Rezaul Haque (2017-3-60-064)
Katura Gania Khushbu(2017-3-60-074)
Md. Sajjad Hoissain(2015-3-60-035)

Date of submission
5th May,2020
Problem 1:
Draw the block diagram, truth table, equation, and logic diagram of a 8-to-1-line multiplexer.

Problem Statement:
The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational circuit with
more than one input line, one output line and more than one select line. It allows the binary information
from several input lines or sources and depending on the set of select lines , particular input line , is routed
onto a single output line. An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input
select lines S2 through S0 and a single output line Y. Depending on the select lines combinations,
multiplexer decodes the inputs.

Design and Analysis:

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that enable or disable
the multiplexer. Since the number data bits given to the MUX are eight then 3 bits (23=8) are needed to
select one of the eight data bits.

Figure:1

The truth table for an 8-to1 multiplexer is given below with eight combinations of inputs so as to generate
each output corresponds to input.
For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly the data outputs D0
to D7 will be selected through the combinations of S2, S1 and S0 as shown in below figure.
S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

From the above truth table, the Boolean equation for the output is given as
Y = D0 S2’ S1’ S0’ + D1 S2’ S1’ S0 + D2 S2’ S1 S0’ + D3 S2’ S1 S0 + D4 S2 S1’ S0’ + D5 S2 S1’ S0 + D6 S2 S1 S0’
+ D7 S2 S1 S0
From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented
by using 8 AND gates, 1 OR gate and 7 NOT gates as shown in below figure. In the circuit, when enable pin
is set to one, the multiplexer will be disabled and if it is zero then select lines will select the corresponding
data input to pass through the output.

Circuit Diagram:
From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented
by using 8 AND gates, 1 OR gate and 3 NOT gates as shown in below figure. In the circuit, when enable pin
is set to one, the multiplexer will be disabled and if it is zero then select lines will select the corresponding
data input to pass through the output.
Problem 2:
Draw the block diagram, truth table, equation, and logic diagram of a 4-to-1-line multiplexer with active-
LOW enable input

Problem statement:
Multiplexing is the generic term used to describe the operation of sending one or more analogue or digital
signals over a common transmission line at different times or speeds and as such, the device we use to do
just that is called a Multiplexer. A 4-to-1 multiplexer with active low enable input consists four data input
lines as I0 to I3, two select lines as S0 and S1,enable input E0=0 and a single output line Y. The select lines
S1 and S2 select one of the four input lines to connect the output line. The particular input combination
on select lines selects one of input (I0 through I3) to the output.
Design and anlysis:
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 ,enable input E=0 as its active
low and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines. Truth table of 4x1 Multiplexer is shown below.
E S1 S0 Y

0 0 0 I0
0 0 1 I1

0 1 0 I2
0 1 1 I3
From Truth table, we can directly write the Boolean function for output, Y as
Y=E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3
From the above expression of the output, a 4-to-1 multiplexer with active low enable input can be
implemented by using basic logic gates. The below figure shows the logic circuit of 4:1 MUX which is
implemented by four 4-inputs AND gates, three 1-input NOT gates, and one 4-inputs OR gate.

Circuit Design:

In this circuit, each data input line is connected as input to an AND gate and two select lines are connected
as other two inputs to it.If the enable input is zero then the circuit will work . The AND gate output is
connected to with inputs of OR gate so as to produce the output Y.
Problem 3:
Structural Verilog Code for the logic diagram for a 8-to-1-line multiplexer and simulate it using Quartus II
software

Problem statement:
An eight-to-one-line multiplexer is a combinational circuit where one of the eight inputs is connected to
one output. D0, D1, D2… D7 are the eight inputs. There are three select lines S0, S1, and S2 to select input.

Structural Verilog code:

module mux8to1( input in0,in1,in2,in3,in4,in5,in6,in7,s0,s1,s2, output Y);
wire w,x,y,z,s,t,u,v,nots1,nots2,nots3;
not(nots0,s0);
not(nots1,s1);
not(nots2,s2);
and(s,in0,nots0,nots1,nots2);
and(t,in1,nots0,nots1,s2);
and(u,in2,nots0,s1,nots2);
and(v,in3,nots0,s1,s2);
and(w,in4,s0,nots1,nots2);
and(x,in5,s0,nots1,s2);
and(y,in6,s0,s1,nots2);
and(z,in7,s0,s1,s2);
or(Y,s,t,u,v,w,x,y,z);
endmodule
Circuit Diagram:

Simulation result:
Problem 4:
Write Behavioral Verilog code for a 4-to-1-line multiplexer with active-LOW enable input and simulate it
using Quartus II software

Problem statement:
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. Since the
enable input EN has negation symbol at its input in the block diagram, 0 enables device and 1 disables the
device. Since the output line has no negation symbol, when the device is disabled, the output signal IO is
0. When the device is enabled, the device output signal IO follows the data input signal selected by select
lines S1 and S0.

Behavioral Verilog code:

module mux41beh(in,s,e,y );
output y ;
input [3:0] in ;
input [1:0] s ;
input [0:0]e;
reg y;
always @ (in,s,e)
begin
if (e[0]==0&&s[0]==0&s[1]==0)
y = in[3];
else if (e[0]==0&&s[0]==0&s[1]==1)
y = in[2];
else if (e[0]==0&&s[0]l==1&s[1]==0)
y = in[1];
else
y = in[0];
end
endmodule
Simulation result: