INDEX

Sr. Page
No. Experiment Title No. Date Sign

To study basic gates and verify their truth tables.

1 1
To realize Basic gates (AND,OR,NOT) From Universal Gates(
2 NAND & NOR). 3
To design and construct basic flip-flops.
3 6
To design and implement encoder and decoder.
4 7
To design and implement multiplexer.
5 8
To design and implement demultiplexer.
6 9
To design and construct of Synchronous Counter
7 10
To design and construct Asynchronous counter
8 12
To study about full adder & verify its truth table.
9 13
To realize half/full adder and half/full subtractor.
10
a. Using X-OR and basic gates
b. Using only NAND gate
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 Experiment 1

Aim: To study and verify the Truth Tables of AND, OR, NOT.
Theory:
AND, AND, OR and NOT gates are basic gates. XOR and XNOR are universal gates. Basically logic gates are electronic
circuits because they are made up of number of electronic devices and components. Inputs and outputs of logic
gates can occur only in two levels. These two levels are term HIGH and LOW.

AND GATE:- An AND gate has two or more inputs but only one output.

X = A.B

Logic symbol: Truth table:

Input Output
A
1 X A B X
3
2
0 0 0
B
0 1 0

1 0 0

1 1 1

OR GATE: Like an AND gate, an OR gate may have two or more inputs but only one
output. The output assumes the logic 1 state, even if one of its inputs is in logic 1 state

X=A+B

Logic symbol: Truth table:

Input Output
A
1
3
X A B X
2

0 0 0
B
0 1 1

1 0 1

1 1 1

1
NOT GATE : A NOT gate is also known an inverter, has only one input and only one
output. It is a device whose output is always the complement of its input.

Logic symbol: Truth table:

Input Output

A X

0 1

1 0

2
 Experiment 2

Aim: - realization of logic gates using NAND and NOR gates.

Universal gates: - The Nand and Nor gates are called as universal gates, because it is
possible to implement any Boolean expression with the help of only Nand or only Nor
gates.

All gates using Nand Gate:-

1) Not using Nand:-

The Boolean expression for NOT gate is Fig. shows the realization of a NOT gate
using a two i/p NAND gate. As both i/p‟s are connected together we can write i/p
A=B=A
So o/p is given as

But A.A=A by AND law

A
𝐴

2) AND using NAND:-

The Boolean expression for an AND gate is Y=A.B
Taking double inversion,

But
Y=A.B
This equation can be realized using only NAND gate as shown in fig.

A
A.B
B

3) OR using NAND:-

3
 The Boolean expression for an OR gate is Y=A + B
Taking double inversion,

But by DE-Morgan‟s theorem

This is required expression for OR gate

A
A+B

All gates using NOR Gate:-

1) Not using NOR:-

The Boolean expression for NOT gate is Fig. shows the realization of a NOT gate using a two i/p
NOR gate. As both i/p‟s are connected together we can write i/p A=B=A So o/p is given as

But A+A=A by OR law

2) OR using NOR:-
The Boolean expression for an OR gate is Y=A+B
Taking double inversion,

But
Y=A+B

This equation can be realized using only NAND gate as shown in fig.

4
 A A+B

3) AND using NOR:-

The Boolean expression for an AND gate is Y=A.B
Taking double inversion,

But by DE-Morgan‟s theorem

This is required expression for AND gate

A.B

5
 Experiment 3

Aim: To design and construct basic flip-flops.

We are using NAND gates To design and construct a D flip-flop .

Theory:

A flip-flop is a fundamental building block in digital circuits used for storing binary information. There are various
types of flip-flops, such as SR flip-flops, D flip-flops, JK flip-flops, and T flip-flops. These devices are used to store
one bit of data and are crucial in sequential logic circuits. To design and construct a basic flip-flop, you'll need to
understand its truth table, characteristic equations, and how to implement it using logic gates like NAND or NOR
gates.

INPUT OUTPUT

Input 1 Input 2 Output 3

0 0 1

0 1 1

1 0 1

1 1 0

6
 Experiment 4

Aim: To design and implement encoder and decoder.

Design and Implementation of Encoders and Decoders: Encoders and decoders are used to convert data from
one format to another. An encoder takes multiple input lines and produces a binary code as output, while a
decoder does the reverse, taking a binary code as input and selecting one of many output lines based on that
code. To design and implement encoders and decoders, you'll need to understand binary and Gray codes, as well
as the logic gates required to build these circuits.
1. Encoders – An encoder is a combinational circuit that converts binary information in the form of a 2N
input lines into N output lines, which represent N bit code for the input.
2. Decoders – A decoder does the opposite job of an encoder. It is a combinational circuit that converts n
lines of input into 2n lines of output.

7
 Experiment 45

Aim: To design and implement multiplexer.

Theory Multiplexer - Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and as such, the device
we use to do just that is called a Multiplexer. The multiplexer , shortened to “MUX” or “MPX”, is a combinational
logic circuit designed to switch one of several input lines through to a single common output line by the
application of a control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.

Basic Multiplexing Switch

Generally, the selection of each input line in a multiplexer is controlled by an additional set of inputs called
control lines and according to the binary condition of these control inputs, either “HIGH” or “LOW” the
appropriate data input is connected directly to the output. Normally, a multiplexer has an even number of 2 n
data input lines and a number of “control” inputs that correspond with the number of data inputs.

Block Diagram

8
 Experiment 56

Aim: To design and implement demultiplexer.

Theory De-Multiplexer - The demultiplexer is a combinational logic circuit designed to switch one common input
line to one of several separate output lines. The data distributor, known more commonly as a Demultiplexer or
“Demux” for short, is the exact opposite of the Multiplexer we saw in the previous tutorial. The demultiplexer takes
one single input data line and then switches it to any one of a number of individual output lines one at a time.

Demultiplexer Output Line Selection :

Some standard demultiplexer IC ś also have an additional “enable output” pin which disables or prevents the input
from being passed to the selected output. Also some have latches built into their outputs to maintain the output
logic level after the address inputs have been changed. However, in standard decoder type circuits the address
input will determine which single data output will have the same value as the data input with all other data outputs
having the value of logic “0”.

Block Diagram:

9
 Experiment 67

Aim: To design and construct of Synchronous Counter

Theory : the Synchronous Counter, the external clock signal is connected to the clock input of EVERY individual
flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the
same time giving a fixed time relationship. In other words, changes in the output occur in “synchronisation” with
the clock signal. The result of this synchronisation is that all the individual output bits changing state at exactly
the same time in response to the common clock signal with no ripple effect and therefore, no propagation delay.

Definition: Synchronous Counters are so called because the clock input of all the individual flip-flops
within the counter are all clocked together at the same time by the same clock signal.

Example : Consider a counter that can count mod 4 or mod 8 is decided by mode control input (say S). If S= 0,
then it will work as mod 4 counter, if S=1 it will perform down counting. For the designing of this type of counter
23= 8(because 3 bits are required for counting up to 7) i.e three FF are required. Here T FF is used. The state
diagram is showing in the below picture.

10
In this, if the counter state is below 011, the value of S can be 0 or 1 because in mod -4 or mod 8 the counting
sequence up to 011 is same in both the situation is the same. So the value of S can be 0 or 1. The transition from
011 to 000 takes place if S= 0 and the counter will reset. The transition from 011 to 100 takes place if S= 1. After
that, the value of S can be 0 or 1 until the state 000 arises. Circuit excitation table : It shows the present state of
the FF and the next state after the clock pulse applied and the input value. Here T FF is used. So the value of
T(toggle) input of FF is 1 only if the corresponding state output value changed from 0 to 1 or 1 to 0. Otherwise, it
remains the same. The below table is according to the required counting sequence. Q - means Present state Q* -
means next state.

Circuit Diagram

11
 Experiment 8

Aim: To design and construct Asynchronous counter.

Theory: Asynchronous counters are those whose output is free from the clock signal. Because the flip flops in
asynchronous counters are supplied with different clock signals, there may be delay in producing output. The
required number of logic gates to design asynchronous counters is very less. So they are simple in design. Another
name for Asynchronous counters is “Ripple counters”. The number of flip flops used in a ripple counter is
depends up on the number of states of counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is
called “Modulus” or “MOD” of the counter.
Asynchronous Counter Basics

By this, we can conclude that – If there are n FFs then the output frequency will be divide by 2n. Also generate 2n
unique states. So the frequency division basically forms counting state. Here we are seeing that the output of the
1st FF act as clock for 2nd FF. Suppose the FF takes 30ns for generating output(i.e. propagation delay because of
gates). Therefore, the output of second FF will be obtained after 60 ns. So the propagation delay is ripples
through the FFs and becomes more when the number of FFs increases. Therefore, asynchronous counter are too
slow for generating big counting. As we know, when the output state (i.e. Q) of previous FF is feed as clock to next
FF then the counter will perform up counting as you seen above(i.e. 0 1 2 3). After 4th -ve edge clock pulse the
sequence will repeat. When the complemented output state (i.e. Q’) of previous FF is feed as clock to next FF
then the counter will perform down counting as you seen below(i.e. 3 2 1 0). After 4th -ve edge clock pulse the
sequence will repeat.

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 Experiment 9

Aim: To study about full adder & verify its truth table.

Theory: Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and
B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is
designated as S which is SUM. A full adder logic is designed in such a manner that can take eight inputs together
to create a byte-wide adder and cascade the carry bit from one adder to the another.

Full Adder Truth Table:

13
 Experiment 10

Aim: To realize half/full adder and half/full subtractor.

a. Using X-OR and basic gates
b. Using only NAND gate

Implementation of Half Adder using NAND gates : Total 5 NAND gates are required to implement half adder.

Implementation of Half Adder using NOR gates : Total 5 NOR gates are required to implement half adder.

Implementation of Half Subtractor using NAND gates : Total 5 NAND gates are required to implement half
subtractor.

Implementation of Half Subtractor using NOR gates : Total 5 NOR gates are required to implement half
subtractor.

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