Subject Code: 20UPH6CC13P2

MAJOR PHYSICS PRACTICAL – VIII

LIST OF EXPERIMENTS

Digital Electronics and Microprocessor: Practicals

SI.No Name of the Experiment Page No

Verification of Logic Gates (AND, OR, NOT, NAND,

1. 1
NOR & EX-OR) and De Morgan’s Theorems using ICs

2. Full adder and Full subtractor using basic logic gates 6

Simplification of Boolean expression using Karnaugh

3. 9
Map.

Verification of the Truth Tables of R-S, Clocked R-S

4. 12
and J-K Flip-Flops.

5. Eight Bit Multiplication and Division using µp 8085. 15

Searching for the Biggest and Smallest Numbers of an

6. 19
Array using µp 8085.

Conversion of a Decimal Number to Hexadecimal form

7. 21
and vice versa using µp 8085

8. FET Characteristics. 26

0
 1. Verification of Logic Gates (AND, OR, NOT, NAND, NOR & EX-OR) and
De Morgan’s Theorems using ICs

Aim :
To verify the truth table of Basic Logic gates AND, OR, NOT, NOR, NAND and the
De Morgan’s Theorems using integrated circuits.

Apparatus Required:

IC Gates
7400 NAND
7402 NOR
7404 NOT
7408 AND
7432 OR

De Morgan’s theorems:

1. Complement of the sum is equal to the product of the complement

A  B  A B
2. Complement of a product is equal to the sum of complements
A B  A  B
Procedure:
The pin configurations of all the ICs are given in appendix B. For all the ICs,
5volts must be given through the pin number 14 and pin number 7 must be connected to
ground.

AND gate:
IC 7408 consists of four 2-input AND gates. If the inputs are given to the pins 1 and 2,
then the output of the AND gate is verified at pin 3.The symbol and the truth table of AND
gate is shown in fig.

A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

1
OR gate:
IC 7432 has four 2-input OR gates. The output of the OR gate is verified at pin 3 if the
inputs are given to the pins 1 & 2.The symbol and the truth table of OR gate is given in Fig.

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

NOT gate:
IC 7404 consists of six NOT gates. If the input is given at pin 1, then the output of the NOT
gate is verified at pin 2. The symbol and the truth table of NOT gate is given in Fig.

A Y=Ā
0 1

1 0

NAND gate:

IC 7400 has four 2-input NAND gates. The inputs may be given to the pins 1&2. The
output is taken from the pin 3. The symbol and the truth table of NAND gate is given in Fig.

A B Y= A.B

0 0 1
0 1 1
1 0 1
1 1 0

2
NOR gate:
IC 7402 consists of four 2-input NOR gates. The inputs may be given to the pins 2&3
and the output is taken from the pin 1. The symbol and the truth table of NOR gate is given in
Fig.
A B Y= A  B

0 0 1
0 1 0
1 0 0
1 1 0

Ex-OR Gate;
IC 7486 has four 2 input EX-OR gates. The inputs are given to the pins 1 & 2 and the
output is taken from the pin 3. The symbol and the truth table of EX-OR gate is shown in
figure.

A B Y=A  B

0 0 0
0 1 1
1 0 1
1 1 0

De Morgan’s Theorems
1. Verification of 1st theorem:
Let A and B be the two inputs. These two inputs are given to the NOT gate. As NOT gate, is an
inverter A, B becomes A and B . Then these two interval inputs are given to an AND gate
whose output will be ‘Q’, and is equal A , B . Now inputs A and B are given directly to an NOR
gate from NOT gate. The output from the NOT gate let be ‘Q2’ and its equal to A B . Now
different values are given to A,B in truth table and the corresponding volts are noted. Thus as a
result it is purified that the complement of sum is equal to the product of complement
i.e.,Q1,Q2
A  B  A B

3
A 1 2
7404

2 7408
3
A B

1 2
B 7404

U3A

2
1
3 A B
A B  A  B
7402

Truth Table:

A B A B Q1= A B Q2 = A B
0 0 1 1 1 1
0 1 1 0 0 0
1 0 0 1 0 0
1 1 0 0 0 0

2. Verification of 2nd Theorem :

As like the first theorem, let A and B be the inputs and they are given to the NOT gate.
After that the inverted inputs are given to the OR gate. The output let be ‘Q1’ and it will be
equal to A B . Now the inputs A and B are connected directly to the NAND gate. Let the
output be noted by ‘Q2’ and its output is equal to A B . Now different values are given to A
and B as per truth table and the corresponding volts are noted. Thus as a result it is purified that
the complement of product is equal to the co sum of complement i.e. Q1= Q2.
A B  A  B

4
A 1 2
7404

1
3
2 7432 A B

1 2
B 7404

1
3
2 7400 A B

Truth Table:

A B A B Q1= A B Q2 = A B
0 0 1 1 1 1
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 0 0

Result:

(i) The truth tables of Basic Logic gates AND, OR, NOR, NOT, NAND verified by using
ICs.
(ii) The De Morgan’s theorems are verified using integrated circuit chips.

5
 2. FULL ADDER AND FULL SUBTRACTOR
Aim:
To construct the full adder and full subtractor circuits using logic gates such as AND,
OR, NOT, EX-OR gates and also verify the truth table.

Apparatus Required:
AND (7408) gate, OR (7432) gate, EX-OR (7486) gate, NOT (7404) gate, etc.,

Circuit diagram:

1. Full Adder:

2. Full Subtractor:

6
Procedure:

The circuit is constructed as shown in the circuit diagram. A full adder is a

combinational circuit that forms the arithmetic sum of the three input bits. It consists of three
inputs and two outputs. Two of the input variables denoted by A and B represent the two
significant bits to be added. The third input C represents the carry from the previous lower
significant position. The two outputs are designed as S for sum and Cy for carry. The truth
table is verified by giving particular inputs.
The circuit is constructed as shown in the circuit diagram. A full subtractor is a
combinational circuit that performs the arithmetic subtraction of three input bits. It consists of
three inputs and two outputs. Two of the variables denoted by A and B represent the two
significant bits to be subtracted. The third input C represents the barrow taken from the next
higher significant position. The two outputs are designed as diff for difference and Br for
barrow. By truth table give particular input and obtain corresponding output.

Truth table:

Full Adder:

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

7
Full Subtractor:

A B C BARROW DIFFERENCE

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Result:

The full adder and full subtractor are constructed using logic gates and their truth tables
are verified.

8
 3. KARNAUGH MAP AND SIMPLIFICATION OF BOOLEAN FUNCTION
Aim:
Simplify the given Boolean function using karnaugh map and verify the result using
logic gates.

Requisites:
Breadboard, IC 7404, 7411, 7432 etc.,

Procedure:
The pin diagram of IC 7411 as shown in figure. Consider the given Boolean function as
shown. The given Boolean function is some of the products. So the canonical table all
construct from the given function. The responding Karnaugh map is also shown. The Karnaugh
map is simplify the functions by quad, pair. So the simplification expression is,
Y  A C D  A BC  ABC  ACD

9
 The corresponding logic circuit are constructed as the given simplification expression is
also shown. The four input’s are taken as A,B,C and D. the input A & C are also connected to
IC7404 so it is become A & C .

The IC 7411 pins 1 and 3 are connected with A and the input B are connected to the IC
7411 pins 4 and 10. the input A are connected to the 5 and 4 of the IC 7411 pins. The C is
connected to pins 2 and 11 also the input D are connected to the IC 7411 pins 13 and 5’. The
output of the IC 7411 pins 12 and 6 are connected to IC 7432 pins 1 and 2. Similarly IC 7411
pins 8 and 6’ are connected to IC 7432 pins 4 and 5 respectively.

The outputs of the OR gate 3 and 6 are connected to the IV 7432 oins 9 and 10. then the
output is taken from pin 8 of the IC 7432. so the output with matching the canonical table. So
the output is verified.

10
Tabular Column:
Input Output
A B C D Y

Result:
The given Boolean function is simplified using Karnaugh map and also verified the
result using Logic gates.

11
 4. Construction and verification of the Truth Tables of R-S, Clocked R-S
and J-K Flip-Flops.
Aim:
To construct and study the working of R-S, Clocked R-S and J-K flip flops using
NAND gate.

Apparatus Required:
IC7400, IC7410, 5V power supply, voltmeter, breadboard, etc.,

Circuit Diagrams:

Pin diagram of IC 7400 Pin diagram of IC 7410

R – S flipflop:

12
Clocked R – S flipflop:

J – K flip flop:

Procedure:
(i). R – S flipflop:
R – S latches have two i/p “S”& “R”. “S” is called “SET” and “R” is called “RESET”.
The “S” i/p is used to produced 0 and Q that is it is stores a binary Q in flipflop. The circuit
diagram and truth table are shown in the figure. It is level triggered. There is multiple
transmission problem called “Racing”.

Truth table:
S R Q OBS Mode
0 0 1 3.43 HOLD
0 1 0 0.18 RESET
1 0 1 3.42 SET
1 1 * 3.41 RACE

13
(ii). Clocked R – S flipflop:
Here two NAND gates device form a NAND gate latch and there are two enable gates 1
& 2 with i/p’s. R – S and clock. The location of clocked R-S latch is given. When clock is low
the o/p of gates 1& 2 goes high and there will not be any change in the o/p of NAND gate. The
gates 1 & 2 are enabled only when clock goes high.

CLK S R Q OBS Mode

0 0 0 3.42 HOLD

0 1 0 0.18 RESET

1 0 1 3.41 SET

1 1 * 3.40 RACE

(iii). J – K flip flop & D flipflop:

Since R – S flipflop contains ambiguous state to dominate the condition. This is done
by connecting R and S with an invertor. It can be observed that the i/p “D” goes directly into
“S” input and invertor into “R” i/p. If D=0, the output is also zero, when the i/p is ‘1’ , output
is also ‘1’. Hence it is called “Delay flipflop” butter gate D – Latch.

Truth Table for J – K flipflop:

CLK J K Qn OBS Mode

0 0 0 0.19 HOLD

0 1 0 0.20 RESET

1 0 1 3.36 SET

1 1 Qn 3.48 TOGGLE

Result:
The flipflop of various types using NAND gate were constructed and their truth table
and the mode of operation is verified.

14
 5. EIGHT BIT MULTIPLICATION AND DIVISION USING µP 8085.

8 Bit Multiplication
Algorithm:
Step 1: Get the multiplier from the memory to the accumulator
Step 2: Transfer the multiplier to B register
Step 3: Get the multiplicand from the memory to the accumulator
Step 4: Transfer the multiplicand to C register
Step 5: Initialize accumulator to zero
Step 6: Clear the D register for strong the carry
Step 7: Add multiplicand in C register to accumulator
Step 8: If the value in accumulator exceeds FFH increment D register by one
Step 9: Decrement the multiplier in B by one
Step 10: If the value in B register is not equal to zero, then go to step 7
Step 11: If the value in B register becomes zero store the lower byte of the result in the
accumulator to memory
Step 12: Store the higher byte of the result in D register memory
Step 13: END.

8 Bit Division:
Algorithm:

Step 1: Get the divisor from the memory to the accumulator

Step 2: Transfer the divisor to B register
Step 3: Get the dividend from the memory to the accumulator
Step 4: Initialize C register with 1 (i.e) FFH to store the quotient.
Step 5: Increment the C register content by one
Step 6: Subtract the divisor in B from the dividend in A
Step 7: If the dividend is greater than the divisor, then go to step 5
Step 8: If the dividend is less than the divisor, add the contents of A & B to get the
reminder
Step 9: Store the reminder in memory
Step 10: Store the quotient in memory
Step 11: End.

15
Procedure:

8 bit Multiplication:

The instruction LHLD 8851H transfer the 16 bit multiplicand from the memory
location 8851 and 8852H to HL pair. By the execution of the instruction XCGH the contants of
H – L pair are exchanged with the contents of DE pair. Thus the multiplicand is placed in DE
pair LXIH makes the initial value of the product equal to zero and is placed in HL pair. The
count is equal to the bits of the multiplier. In this it is 08 and it is placed in register C.
Increment HL pair is done by the instr INXH. Thus the partial product which is in HL pair is
shifted left by one. The Accumulator contains the multiplier and hence it is rotated left by one
bit. The instruction B adds the content of DE pair and HL pair and places the result in HL pair.
DE pair and HL pair contain multiplicand and partial product respectively. Thus the execution
of Add B adds the multiplicand to the partial product and places the sum which is the new
partial product in HL pair. To get the result the program moves in the loop 8 times as there are
8 bit in the multiplier.

8 – Bit Division:

The count in register C is kept as 08. this trial subtraction is done 8 times and an 8 – bit
positions in register L fall vacant. In the vacant bit positions quotient is stored. Note that the
dividend is shifted prier to trial subtraction. The MSB of the dividend should be zero, other it
will be shifted to carry bit. If a problem contains MSB not equal to zero, it will be solved by
splitting it in two parts. Shifting of dividend before subtraction is not done in ordinary division
by pen and paper, but the computer method gives correct result as the numbers are represented
in binary coded hexa decimal system.

16
Program: 8 – Bit Multiplication

Memory Machine
Label Mnemonics Comments
Address Code
4100
21,30,41 LXI H 8850H LOAD IN(NL) PAIR

4103 46 MOV B,M MOVE THE DATA TO B

4104 23 INX H INCREMENT (HL) PAIR

4105 4E MOV C,M MOVE THE DATA TO C

4106 97 SUB A SUBTRACT

4107 80 LOOP ADD B ADD THE DATA WITH B

4108 0D DCR C DECREMENT C

JUMP TO LOOP WHEN

4109 C2, 07, 41 JNZ LOOP
NONZERO

410C 23 INX H INCREMENT (HL) PAIR

410D 77 MOV M,A MOVE THE RESULT TO M

410E 76 HLT HALT

Program 2: 8 – Bit Division

Memory Machine
Label Mnemonics Comments
Address Code
4100 INITIALIZE REGISTER TO
0E,00 MVI C, 00H
STORE QUOTIENT

4102 21, 50, 41 LXI H, 8850H LOAD IN HL PAIR

4105 7E MOV A, M MOVE DIVIDEND INTO A

4106 23 INX H INCREMENT H-L PAIR

4107 46 MOV B , M MOVE DIVISOR INTO B

17
 COMPARE DIVIDEND INTO
4108 B8 LOOP CMP B
DIVISOR
IF DIVIDEND < DIVISOR GO
4109 DA, 11, 41 JC DONE
TO DONE

410C 0C INR C ELSE INCREMENT C

SUBTRACT DIVISOR FORM

410D 90 SUB B
DIVIDEND

410E C3, 08, 41 JMP LOOP GO TO LOOP

4111 23 INX H INCREMENT H-L PAIR

4112 71 MOV M, C MOVE QUOTIENT INTO C

4113 23 DONE INX H INCREMENT H-L PAIR

4114 77 MOV M, A MOVE REMAINDER INTO A

8815 76 HLT HALT

Result:
Input Output
Memory location Data byte Memory location Data byte

4150 05
4152
4151 02

Input Output
Memory location Data byte Memory location Data byte

4150 05 4152 ( Quotient)

4151 02 4153 ( Reminder)

18
 6. SEARCHING FOR THE LARGEST AND SMALLEST NUMBERS IN AN ARRAY
USING µP 8085
Aim:
To find the largest and smallest numbers in an array using µP 8085.

Algorithm:

Step 1: Load ‘N’ bytes in memory whose starting address is in HL register pair.
Step 2: Move the first data from memory to accumulator.
Step 3: Move the second data in memory.
Step 4: Compare the data in A register with the data in M register.
Step 5: If data in A register is smaller/larger than the data in B register go to step 8.
Step 6: Else ‘swap’ the first data with the second data stored in memory.
Step 7: Increment the memory address by one.
Step 8: Decrement the count register C by one.
Step 9: If C register content is not equal to zero, go to step 7.
Step 10: End.

Address Op-code Label Mnemonics Operands Comments

Address for count

4100 21, 50, 41 LXI 4150H
in HL pair
Load C register
4103 4E MOV C, M
with required count
Address of first
4105 23 INX H
number in HL pair
1st number in
4106 7E MOV A, M
accumulator.

4107 OD DCR C Decrement count

Address of the next

4108 23 LOOP INX H
number
Compare next no.
4109 BE CMP M with previous
maximum
No, larger/smaller
410C D2, OD, 41 JNC/JC AHEAD no, is in
accumulator. go to

19
 AHEAD

Yes, get
410D 7E MOV A,M larger/smaller no.
in accumulator.

410E OD AHEAD DCR C Decrement count

410F C2, 07, 41 JNZ LOOP C 0, go to loop

Store result in
4110 32, 80, 41 STA 4180
4180H

4111 76 HLT STOP

NOTE: JNC to find largest numbers and JC for smallest numbers

Data:

Input Output
Largest Smallest
Address Data Address
Number Number
4150 4180
4151
4152
4153
4154
4155
4156
4157
4158
4159

20
 7. CONVERSION FROM DECIMAL TO HEXADECIMAL SYSTEM USING INTEL
8085 MICROPROCESSOR
Aim:
To convert the decimal number into hexadecimal number and hexadecimal number into
decimal number using Intel 8085 microprocessor.

Algorithm:
Decimal to Hexadecimal
Step 1: Start the program
Step 2: The decimal value or data load in the accumulator from pointer 4150
Step 3: The accumulator data transfer to B register
Step 4: AND logic using between 0F and decimal data in B register
Step 5: The next decimal data to take the C register from accumulator
Step 6: Transfer the decimal data B register to accumulator
Step 7: Three times using rotating right in accumulator
Step 8: Ex-OR logic using in accumulator
Step 9: The logic result is compare to B register data
Step 10: If zero to add the data to C register, if not zero add the data to 0A
Step 11: The result and conversion hexadecimal data store pointer 4151
Step 12: Program end.

Program for Decimal to Hexadecimal Conversion

Address Op-code Label Mnemonics Operands Comments

4100 3A 50 41 LDA 4150H Load content of
Memory to Acc.
4103 47 MOV B,A Move the data from
A to reg B
4104 E6 0F ANI 0FH 0FH ANDed with
content of Acc.
4106 4F MOV C,A Move the content
Acc. to C register

21
4107 78 MOV A,B Move the content
of B to A register
4108 0F RRC Rotate right
through carry of
content Acc.
4109 0F RRC Rotate right
through carry of
content Acc.
410A 0F RRC Rotate right
through carry of
content Acc.
410B 0F RRC Rotate right
through carry of
content Acc.
410C E6 0F ANI 0FH 0FH ANDed with
the content of Acc.
410E 47 MOV B,A Move the content
of register A to B
410F AF XRA A Ex-ORed the
content of A itself
4110 B8 CMP B Compare the
content in register
B with A
4111 CA 1A 41 JZ LOOP1 If zero then goto
LOOP1
4114 C6 0A LOOP 2 ADI 0AH 0AH ANDed with
the content of Acc.
4116 05 DCR B Decrement on B
register
4117 C2 14 41 JNZ LOOP2 If no zero jump to
LOOP2
411A 81 LOOP 1 ADD C Add the content C
with the content of
Acc.
411B 32 51 41 STA 4151H Store the data from
Acc. to Mem.
411E 76 HLT Program Halt

22
Data:

Input Output
Address Decimal Address Hexadecimal
4150 4151
4150 4151
4150 4151
4150 4151
4150 4151

Hexadecimal to Decimal
Algorithm:
Step 1: Program Start
Step 2: The data load into the H-L pair register
Step 3: The data load 0000 into the B-C pair register
Step 4: Move the content of memory to accumulator
Step 5: Subtract the data from the content of accumulator
Step 6: If carry add data with the content of accumulator. If not carry increment on B
register
Step 7: If carry found subtract the data 0A from the content of accumulator. If not carry
found increment on register C.
Step 8: Add data 0A with the content of accumulator
Step 9: Increment on H-L pair register
Step 10: Move the content of B register into memory.
Step 11: Move the accumulator content into B register
Step 12: Move the content of C register unto accumulator
Step 13: four times using rotating left in accumulator
Step 14: Add the content of B register
Step 15: Increment on H-L pair register
Step 16: Move the content of accumulator into the memory content
Step 17: The program End.

23
Program for Hexadecimal to Decimal Conversion

Address Op-codes Label Mnemonics Operands Comments

Load data into H-L pair

4100 21 50 41 LXI H,4150H
register
Load data 0000H into B-C
4103 01 00 00 LXI B,0000H
pair register
Move the content of
4106 7E MOV A,M
memory into Acc.
Subtract the data 64H
4107 D6 64 LOOP 1 SUI 64H
from the content of Acc.
4109 DA 10 41 JC LOOP 2 Jump if carry found

410C 04 INR B Increment on B register

410D C3 07 41 JMP LOOP 1 Jump to LOOP 1

Add data 64H with the
4110 C6 64 LOOP 2 ADI 64H
content of Acc
Subtract the data 0AH
4112 D6 0A LOOP 3 SUI 0AH
from the content of Acc.

4114 DA 1B 41 JC LOOP 4 Jump if carry found

4117 0C INR C Increment on C register

4118 C3 12 41 JMP LOOP 3 Jump to LOOP 3

Add data 0AH with the

411B C6 OA LOOP 4 ADI 0A
content of Acc

411D 23 INX H Increment on H-L pair

Move the content of B into

411E 70 MOV M,B
Memory
Move the content of Acc
411F 47 MOV B,A
into B register
Move the content of C into
4120 79 MOV A, C
A register
Rotate left through carry of
4121 07 RLC
content A
24 Rotate left through carry of
4122 07 RLC content A
 Rotate left through carry of
4123 07 RLC content A
Rotate left through carry of
4124 07 RLC content A
Add the content of B with
4125 80 ADD B
Acc.

4126 23 INX H Increment on H-L pair

Move the content of Acc

4127 77 MOV M,A
into Memory

4128 76 HLT Halt

Data:

Hex Input Decimal Output

Address Data Address Data

4150 70 4051 01 Hundreds
4052 12 Tens
4150 96 4051 01 Hundreds
4052 50 Tens
4150 CD 4051 02 Hundreds
4052 05 Tens

Result:

The conversion of a decimal number to hexadecimal form and vice versa are written
using µP 8085, executed and outputs are verified.

25
 8. FET Characteristics

Aim:

To study the characteristic of a FET and to determine its parameters.

Apparatus required:

FET (BFW10), voltmeters 2 (0-10V& 0-3V), milli ammeter (0-25 mA), connecting
wire etc…

Formula:
 V 
Drain resistance rd   ds  
 I d V gs
 I 
Mutual conductance g m   d  mho
 V 
 gs Vds
Amplification facto   rd  g m

Where
Vds → Voltage across drain-source (V)
Id → Drain current (ampere)
Vgs → Voltage across drain-source (V)

Circuit diagram:

26
Procedure:
The circuit is connected as shown in the fig. At first by varying the value of V DS
and VGS at constant note the ID current . Now the value of VGS is increased as 0.5 v gradually
increased the VDS and the corresponding currents are noted.. The experiment is repeated for
VGS AS 1 v and the current will be noted.
Now the graph is plotted between VDS and I D as constant VGS , we obtain
three curves . From the graph we calculate the parameters,

 V 
i) Drain resistance rd   ds  
 I d V gs

 I 
ii) Mutual conductance g m   d  mho
 V 
 gs Vds

iii) Amplification facto   rd  g m

Drain current Id (mA)

Vds
(volt) Vgs= Vgs= Vgs=

0
0.5
1.5
2
2.5
.
.
.
.

27
Model graph

7 Vgs=0 volt

5
Id(mA)

4
Vgs=-1 volt

Vgs=-2 volt
1

pinch-off voltage(2.42 V)
0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
Vds(volt)

Result:
The characteristics of the given FET is studied and then its parameters are calculated
and the graph is drawn
1. Drain resistance (Rd) =
2. Mutual conductance (gm) =
3. Amplification factor(
28