CSE 231L

Digital Logic Design Lab

 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 01: Digital Logic Gates and Boolean Functions
_____________________________________________________
A. Objectives
Study the basic logic gates - AND, OR, NOT, NAND, NOR, XOR.
Acquaint with the representation of Boolean functions using truth tables, logic diagrams and Boolean algebra.
Prove the extension of inputs of AND and OR gates using the associate law.
Familiarize with combinational logic circuit.

B. Equipments
IC 7400 Quadruple 2-input NAND gates
IC 7402 Quadruple 2-input NOR gates
IC 7404 Hex Inverters (NOT gates)
IC 7408 Quadruple 2-input AND gates
IC 7432 Quadruple 2-input OR gates
IC 7486 Quadruple 2-input XOR gates
Trainer Board

C. Theory
C.1. Digital Logic
Logic Gates
Logic gates are the elementary building blocks of digital circuits. They perform logical operations of one or more logical
inputs to produce a single output. Digital logic gates operate at two discrete voltage levels representing the binary values
0 (logical LOW) and 1 (logical HIGH). Table C.1 provides a brief description of the basic digital logic gates, their
corresponding IC numbers and circuit symbols.

Gate Description IC # Symbol

AND Multi-input circuit producing an output of 1 if all inputs are 1. 7408

Multi-input circuit producing an output of 1 when any of its inputs is

OR 7432
1.

Single-input circuit that inverts the input (also called an Inverter).

NOT 7404
The output is 0 if the input is 1 and vice versa.

NAND AND followed by an Inverter 7400

NOR OR followed by an Inverter 7402

The Exclusive-OR or Ex-OR is a two-input circuit that produces an

XOR 7486
output of 0 is both inputs are same and 1 if the inputs are different.

Table C.1 Logic gates

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Truth Table

=
00 0
01 0
10 0
11 1

Table C.2 Truth table of AND

A truth table shows all output logic levels of a logic circuit for every possible combination of inputs. For example, Table
C.2 shows the truth table for a two-input AND gate.

Boolean Algebra

Boolean algebra is a branch of mathematical logic that formalizes the relation between variables that take the truth values
of true and false, denoted by 1 and 0 respectively. It is fundamental in the development of digital electronics. Digital
electronics networks are generally expressed as Boolean functions. Discrete voltage levels are used to represent the
truth values. Postulates and theorems of Boolean algebra are given in Table C.3.

Postulates and Theorems Name

+0= 1= Identity
+ =1 =0
+ = =
+1=1 0=0
= Involution
+ = + = Commutative
+ + = + + = Associative
+ = + + = + + Distributive
+ = = + De Morgan
+ = + = Absorption
Table C.3 Laws of Boolean algebra

Combinational Logic

Combination logic refers to digital networks where the output is solely dependent on the current input(s) and is not
affected by previous states. The analysis of combination logic requires writing the Boolean functions for each element of
the circuit, producing their truth tables, and subsequently combining each function for the final output and truth table.

C.2. Integrated Circuits

Integrated Circuits

IC - Integrated Circuit
Figure C.1 illustrates an example IC. The basic rule for most ICs is that there is polarity mark, such as the half-moon
notch shown in the figure. Another common polarity mark is a small dot, triangle or tab by pin 1. The rule is to move
counter-clockwise around the chip from the polarity mark while numbering the pins starting at 1. Sometimes no direct
mark may be present, in which case the pin numbers can be inferred simply from the orientation of the text inscribed on
the IC.

Figure C.1 Example IC configuration

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7400 Series Integrated Circuits

TTL - Transistor-Transistor Logic

The 7400 series of digital logic ICs represents the most popular family of TTL ICs. Most such modern ICs have been
replaced with CMOS. To find the IC number on the chip, simply read the numbers off it ignoring the letters. For example,
74HC04N is the 7404 Hex Inverter IC where the HC denotes it is a high-speed CMOS variant of the TTL circuit.

Figure C.2 shows the pin configurations of the basic logic gate ICs. Figure C.2(a) shows the pin configuration of IC 7400
quadruple 2-input NAND gates. The pin configurations of ICs 7408 AND, 7432 OR and 7486 XOR are same as IC 7400
NAND. Figure C.2(b) and (c) show the pin configurations of ICs 7404 hex inverters and 7402 quadruple 2-input NOR
gates respectively. Note that the input and output pins of the NOR gates are reversed compared to the NAND gates. For
all of the above ICs, pin 7 is designated GND (logical LOW) and pin 14 is connected to +5 V as V CC (logical HIGH).

Figure C.2 Schematic of (a) 7400 NAND, 7408 AND, 7432 OR and 7486 XOR, (b) 7404 NOT, and (c) 7402 NOR ICs

D. Procedure
D.1. Introduction to Basic Logic Gates
1. Place the 7408 AND IC on the breadboard.
2. Connect the VCC and GND pins of the IC to the +5 V and GND ports of the trainer board respectively.
3. Label the pin numbers of the inputs and output of the gate in Figure D.1, using the pin configurations in Figure C.2.

Figure D.1 Pin configurations of gates in ICs

4. Connect the gate.

a. Connect each input of the gate to a toggle switch on the trainer board.
b. Connect the output of the gate to an LED on the trainer board.

5. Apply all combinations of inputs by turning the toggle switches on (1) and off (0), and record if the LED is on (1) or
off (0) as the output of the gate. Record your results in Table D.1
Input AND OR NAN9D XOR NOR
Input NOT

00

01 0

10 1

11

Table D.1 Truth table of logic gates

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6. Replace the AND IC with OR, NAND and XOR ICs without changing the connections and repeat step 5 for each.
7. Repeat steps 1-5 for the NOT and NOR ICs.

D.2. Extension of Inputs of AND and OR

1. Complete the truth table for the 3-input AND gate in Table D.2.

= = + +
000

001

010

011

100

101

110

111

Table D.2 Truth table of 3-input AND and OR

2. Using the associative law given in Table C.3, express the 3-input function using two 2-input AND gates in Table D.3.

Table D.3 Associative law

3. Label the pin numbers in Figure D.2, using the pin configurations in Figure C.2.

Figure D.2 Extension of inputs of AND and OR gates

4. Connect the circuit.

5. Connect the output to an LED and verify it using the truth table.
6. Repeat steps 1-5 for the 3-input OR gate.

D.3. Implementation of Boolean Functions

= + +
1. Complete the truth table for the implicants 1 = , 2 = and 3 = in Table D.4.

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2. Complete the truth table for the function in Table D.4.

000

001

010

011

100

101

110

111

Table D.4 Truth table of logic gates

3. Label the pin numbers for the NOT, AND and OR gates of the function in Figure D.3, using the pin configurations in
Figure C.2.

Figure D.3 Circuit diagram for the Boolean function

4. Connect the input to a NOT gate using the pins assigned in step 3 and check the output via an LED.
5. Wire upimplicant 1 .
6. Connect the output of 1 to an LED and verify it using the truth table.
7. Connect the input to a NOT gate using the pins assigned in step 3 and check the output via an LED.
8. Wire up implicant 2 .
9. Connect the output of 2 to an LED and verify it using the truth table.
10. Wire up implicant 3 .
11. Connect the output of 3 to an LED and verify it using the truth table.
12. Connect the outputs of the three implicants as inputs to the OR gates (using the associative law).
13. Connect the output to an LED and verify the function using the truth table.

E. Questions
1. Is it possible to make a 3-input NAND or NOR gate with 2-input NAND or NOR gates? Justify your answer.

F. Report
1. Simulate the combinational logic circuit of Experiment 01( Figure D.3) in Logisim and attach the circuit in your lab
report, showing only the instance when the input = 010.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 02: Combinational Logic Design
_____________________________________________
A. Objectives
Familiarize with the analysis of combinational logic network.
Learn the implementation of networks using the two canonical forms.
Devise combinational circuits using universal logic.
Acquaint with basic binary arithmetic circuits the half and full adders.

B. Theory
Concise theory pertinent to lab experiments to go here to aid students in performing experiments with minimal
supervision. For example, topics for this lab should include definition and steps to:
Analysis of combinational logic design Min terms and max terms
Canonical Forms
Universal gates bubble pushing, De theorem.

C. Experiment 1: Analysis of a Combinational Logic Circuit

C.1. Equipments:
Trainer Board
1 x IC 7411 Triple 3-input AND gates
1 x IC 7432 Quadruple 2-input OR gates
1 x IC 7404 Hex Inverters (NOT gates)
C.2. Procedure
Input
Min term Max term
Reference

0 000 0
1 001 1
2 010 1
3 011 0
4 100 0
5 101 0
6 110 1
7 111 0
Table C.1 Truth table to a combinational circuit

1. Write down all the min terms and max terms of three inputs in Table C.1.
st nd
2. Write down the function in 1 and 2 Canonical Forms in Table C.2.
Shorthand Notation Function
st
1 Canonical
Form
nd
2 Canonical
Form

st nd
Table C.2 1 and 2 canonical forms of the combinational circuit of Table C.1
3. Draw the circuits in the space provided below, clearly indicating the pin numbers corresponding to the relevant
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 ICs.

st
1 Canonical Form

nd
2 Canonical Form

st nd
Figure C.1 1 and 2 canonical circuit diagrams of the combinational circuit of Table C.1

st
4. Construct the 1 canonical form of the circuit and test it with the truth table.
i. Connect one min term at a time and check its output.
ii. Once all min terms have been connected and verified, OR the min terms for the function output.

C.3. Report
st nd
Simulate above two circuits (1 and 2 canonical forms) in Logisim.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 03: Universal Gates
______________________________________________
A. Equipments

Trainer Board
IC 7400 Quadruple 2-input NAND gates
IC 7402 Quadruple 2-input NOR gates

B. Procedure

Figure B1: NAND as a universal gate

1. Verify each of the NAND gate equivalent circuits in Figure B1 to perform the same operations of the basic gates.
2. Design, construct and test the implementations of XOR and XNOR gates using NAND gates only. Show the circuits in
Figure D1 (Section D), clearly labeling the pin numbers.
3. Design, construct and test the implementations of NOT, AND, OR, XOR and XNOR gates using NOR gates only.
Show the circuits in Figure D2 (Section D), clearly labeling the pin numbers.

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 Figure B2: A combinational circuit

4. Complete the truth table for the circuit in Figure B2 in table D1 (Section D)
5. Convert the circuit in Figure B2 to a NAND gate equivalent circuit, showing the steps involved and clearly labeling the
pin numbers in the final circuit design. Show your work in Figure D3 (Section D).
(i) Replace each of the gates with its NAND gate equivalent in step 1.
(ii) Identify any inversions that are compensated (i.e. one inverter followed by another) in step 1 and redraw the
final circuit in step 2.
6. Validate the operation of the universal gate circuit from the truth table.
C. Report
2. Convert the combinational circuit of Figure B2 to a universal gate circuit using NOR gates only and simulate it
using Logisim. You will need to convert the circuit to 2nd Canonical form and then minimize it before performing this
conversion. Provide the Logisim circuit schematic with your report.

D. Experimental Data

Figure D1: Implementation of XOR and XNOR using NAND gates

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 NOT AND OR

XOR XNOR

Figure D2: Implementation of NOT, AND, OR, XOR and XNOR using NOR gates

A B C I1 = A C I2 = B F = I1 + I 2

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Table D1: Truth table of combinational circuit in Figure B2

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 Step 1

Step 2

Figure D.3 Universal (NAND) gate implementation of the circuit of Figure B2

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 04: Combinational Logic Design
_____________________________________________

A. Objectives
Design a complete minimal combinational logic system from specification to implementation.
Minimize combinational logic circuits using Karnaugh maps.
Learn various numerical representation systems.
Implement circuits using 1st and 2nd canonical minimal forms.

B. Apparatus
Trainer board
Logic gate ICs: 2- and 3-input AND, OR, NAND

C. Procedure
Design of BCD to Excess-3 converter: Design, minimize and implement a digital logic system where an input in binary
coded decimal (BCD) in converted and displayed in Excess-3.
1. Complete the truth table (Table E1, Section E) for the BCD to Excess-3 converter.
2. Identify the inputs and outputs from the truth table and complete the system analysis (Table E2, Section E).
3. Complete the K-maps (Figure E1, Section E) to find the minimal 1st canonical functions of each output variable.
4. Draw the minimal circuit showing the pin configurations (Figure E2, Section E).
5. Implement and test the circuit on the trainer board.
Connect the 4 inputs to the BCD inputs on the trainer board to display the input digits on the seven-segment display.
6. Convert, implement and test the circuit in the suitable universal gate format. Show the circuit with pin configurations
(Figure E3, Section E).

D. Report
1. Design and simulate the minimal NOR logic implementation of Excess-3 to BCD converter.

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E. Experimental Data

Binary Coded Decimal Excess-3

(BCD)

A B C D W X Y Z

Table E1: Truth table - BCD to Excess-3

Number of inputs bits: Input variables:

Number of outputs bits: Output variables:

Table E2: System analysis

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Figure E1: K-M

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Figure E2: Minimal 1st canonical circuit of BCD to Excess-3 converter

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Figure E3: Minimal universal gate implementation of BCD to Excess-3 converter

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 05: Binary Arithmetic
_____________________________________________

A. Objectives
Minimize combinational logic circuits using Karnaugh maps.
Learn various numerical representation systems.
Implement circuits using 1st and 2nd canonical minimal forms.
Implement circuits using universal logic

B.Theory
Topics covered: Binary adder using IC, Ripple through carry 8-bit adder, Binary adder-subtrractor, BCD adder

C. Experiment 1: Binary Adder-Subtractor

C.1 Apparatus
Trainer board
1 x IC 7483 4-bit binary adder
1 x IC 7486 quadruple 2-Input XOR gates
C.2 Procedure

Figure C.1 4-bit adder-subtractor

1. Construct the 4-bit adder-subtractor circuit of Figure C.1.

2. Complete the operations in Table C.1.
i. For each operation, convert the first operand to binary as A, and the second operand as B.
ii. Write down the value of M required for the operation.
iii. Note down the values of the output carry C4 and data output S4-S1. Verify the results.

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 Operation M A B C4 S4 S3 S2 S1

7+5

4+6

9 + 11

15 + 15

7 5

4 6

11 2

15 15

Table C.1

C.3 Report
1. Comment on the use of the XOR gates and the M bit of the 4-bit adder-subtractor.
2. Write down your observations of the results from the addition and subtraction operations performed.

D Experiment 2: Ripple-Through-Carry Adder

D.1 Apparatus

Trainer board
2 x IC 7483 4-bit binary adder

D.2 Procedure
1. Deduce the circuit diagram of an 8-bit ripple-through-carry binary adder using two 4-bit adders, clearly showing the pin
numbers.
2. Construct the 8-bit adder.
3. Complete the operations in Table D.1.

Overflow
Operation A B Sum
Carry

7+5

18 + 19

72 + 83

129 + 255

Table D.1

D.3 Report
1. Comment on your observations of the results.
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E Experiment 3: BCD Adder

E.1 Apparatus
Trainer board
2 x IC 7483 4-bit binary adder
1 x IC 7408 quadruple 2-Input AND gates
1 x IC 7432 quadruple 2-Input OR gates

E.2 Procedure
1. Complete Table E.1 for the BCD sum.

2. Construct the circuit of Figure E.1

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 Figure E.1

3. Verify the outputs in Table E.2

Overflow
Operation A B Sum
Carry

9+0

9+1

9+2

9+3

9+4

9+5

9+6

9+7

9+8

9+9

Table E.2

E.3 Report
1. Derive the circuit for the BCD adder.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 06: BCD to seven segment decoder
_____________________________________________
A. Introduction:

An ABCD to seven segment decoder is a combinational circuit that converts a decimal digit in BCD to an
appropriate code for the selection of segments in an indicator used to display decimal digit in a familiar
form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segments in the
display, as shown in figure (a). The numeric display chosen to represent the decimal digit is shown in
figure (b).

Each element (a, b, c, d, e, f, g) of the seven segment display is turned on when a logic low is applied
to its corresponding input pin.

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B. Equipments:

Trainer board
IC 7447, resistors, seven segment display
Wires for connection

Pin Configuration of 7447:

Circuit Diagram:

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 Truth Table:

Decimal Inputs Outputs

D C B A a b c d e f g

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

C. Report
1. Draw logic diagram for the above truth table.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 07: Introduction to Multiplexers & 3 to 8 line Decoder
_____________________________________________________
A. Introduction:

Multiplexers have the most important attributions of digital circuitry in communication hardware.
These digital switches enable us to achieve the communication network we have today. In this
experiment the students will have to construct MUX (multiplexers) with simple logic gates.

B. Equipments:
Trainer board
IC 7404, IC 7411, IC 7432
Wires for connection

JOB 1:

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Y= I0S1'S0' + I1S1'S2 + I2S1S2' + I3S1S2

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Circuit diagram:

Implement this function using 4:1 MUX; F (A, B, C) = (0, 1, 5, 7) [take A as input]

Procedure:

1) Write the truth table for 4:1 MUX.

2) Write the Boolean function for the output logic.
3) Draw the logic diagram to implement the Boolean function.
4) Select the required ICs.
5) Observe and note the output logic for all combination of inputs.
JOB 2:

Implement this function using 8:1 MUX (IC 74151);

F (A, B, C, D) = (0, 1, 3, 5, 8, 9, 14, 15) [take A as input]

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JOB 3:

3 to 8 line Decoder:

It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND
gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it takes
a 3-bit binary input code and activates one of the 8(octal) outputs corresponding to that code. The truth
table is as follows:
Procedure:

Implement a 3 to 8 line decoder by using IC 74138.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 08: Introduction to Flip-flop and Registers
A. Introduction:

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-
flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or
more control inputs and will have one or two outputs. It is the basic storage element in sequential logic.
Flip-flops and latches are a fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems.

design JK flip-flop, T flip-flop and D flip-flop in this experiment.

Job -1:

Design of a J-K Flip-flop using AND and NOR gates only.

Procedure:

1. The logic diagram to implement J-K Flip-flop.

2. Fill up the Table with different combination of inputs.

J K Q
1 0
0 0
0 1
0 0
1 1
1 0
1 1

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Job -2:

Design of a T Flip-flop using a J-K Flip-flop.

Procedure:

1. Draw the logic diagram to implement T Flip-flop.

2. Fill up the Table with different combination of inputs.

T Q
0
1

Job -3:

Design of a D Flip-flop using a J-K Flip-flop.

Procedure:

1) Draw the logic diagram to implement D Flip-flop.

2) Fill up the Table with different combination of inputs.

D Q
0
1
B. Register:

A register is a group of flip-flops. Each flip-flop is capable of storing one bit of information. An n-bit register contains a
group of n flip-flops capable of storing n bits of binary information. In addition to flip- flops, a register may have
combinational gates that perform certain data processing tasks. In broadest definition, a register consist of a group of
flip-flops and gates that effect their transition. The flip-flop holds binary information and the gates determine how the
information is transferred into the registers.

A register is capable of shifting its binary information either to its right or its left is called a shift register. The logical
configuration of a shift register consists of a chain of flip-flops connected in cascade, with the output of one flip flop
connected to the input of the next flip-flop. All flip-flops receive a common pulse which causes the shift from one stage to
the next.

In this experiment, you will use D flip-flop to construct a right shift register.

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Equipments:
Trainer Board
IC 7474 (D flip-flop)
Wires for connection.

Layout diagram of IC 7474:

Circuit Diagram:

State Table:

States Input Output

Initial State X XXXX
T1 1 1XXX
T2 0 01XX
T3 1 101X
T4 0 0101

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 Procedure:

1. Collect the required equipments.

2. Construct the circuits according to the given diagrams and pin configuration of the IC7474.
3. Observe the outputs.

C. Report:
Design a 2 bit up counter using D Flip Flop.

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 North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 09: Synchronous Sequential Circuits
_______________________________________________
A. Objective:

To design, build and test synchronous sequential circuits.

B. Equipments:
IC JK master-slave, T and D flip-flops
IC type 7408 quad 2-input AND gates
IC type 7404 NOT gates

Procedure:

1. Synchronous Sequential circuits:

a) Design, construct and test a sequential circuit whose state is shown in
Figure.1. Use JK, T and D flip-flops in the design.

00

1/1
0/0
1/0

01 10 0/0
1/1

Figure: 1

The circuit has two flip-flops A, B, one input x and one output y. The circuit is to be
designed by treating the unused states as care conditions. The final circuit must be
analyzed to ensure that it is self-correcting. If not suggest a solution.

b) Complete the excitation table shown in Table 1

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Present state Input Next state Output Flip-flop input functions
A B X A B Y JA KA JB KB
0 0 0 0 1 0 0 X 1 X
0 0 1 1 0 1 1 X 0 X
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 1. For JK Flip Flop Input Functions

Flip-flop input
Present state Input Next state Output functions
A B X A B Y DA DB
0 0 0 0 1 0 0 1
0 0 1 1 0 1 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2. For D Flip Flop Input Functions

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 Flip-flop input
Present state Input Next state Output functions

A B X A B Y TA TB
0 0 0 0 1 0 0 1
0 0 1 1 0 1 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 3. For T Flip Flop Input Function

c) Using Karnaugh maps obtain minimal expressions for the flip-flop input functions
JA, KA, JB, KB, DA, DB, TA, TB.
d) Build the circuits and check the output to verify the state table values.

C. Report:

Simulate the circuits using Logisim.

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