CEG2136 Midterm Exam 2016

CEG2136: Computer Architecture I

CEG2536: Architecture des Ordinateurs I

MIDTERM EXAMINATION SOLUTIONS

Professors: Voicu Groza, Rami Abielmona and Burak Kantarci

Duration: 1 hour and 30 minutes October 21, 2016 @ 19:30

Question 1 (20 points)

The 2's complement representation is used in an 8-bit register which contains the binary value
01001001.
a. What is the register value after an arithmetic shift left? Give your result both in binary
and decimal.
R (before asl) 0 1 0 0 1 0 0 1
R (after asl) 1 0 0 1 0 0 1 0
R before = (01001001)2 = (+73)10
R after = (10010010)2 = -x, with x= |10010010| = 2’s compl. (10010010)2 =
1101101+1=01101110=2+4+8+32+64 R after = (-110)10
b. Starting again from the initial number 01001001, determine the register value after an
arithmetic shift right, both in binary and decimal.
R (before asr) 0 1 0 0 1 0 0 1
R (after asr) 0 0 1 0 0 1 0 0

R after = (00100100)2 = (+36)10

c. Starting again from the initial number 01001001, determine the register value after a
circular shift right, both in binary and decimal.
R (before cir) 0 1 0 0 1 0 0 1
R (after cir) 1 0 1 0 0 1 0 0

R after = (10100100)2 = (-92)10

d. Is there any overflow in any of these three operations? Justify your answer.
How would a computer detect overflows in these operations?

Yes, overflow only occurs in part a) where an asl operation causes the msb (sign bit) to
change (from 0 to 1).
This can be detected by EXOR’ing the 2 most significant bits where overflow would be
detected if the bits are different.

1
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

Question 2 (25 points)

Design a 3-bit multi-function bidirectional shift register whose function is described in the
following table, where M and N are two control bits.
Using the proper digital components (encoders, decoders, multiplexers, etc.), logic gates, and D
flip-flops, draw a detailed diagram of the logic circuit of the register.

Clock M N Operation I2 Q2
↑ 0 0 Store current value / No change I1 Q1
↑ 0 1 Decrement by 3 I0 Multi
↑ 1 0 Load external inputs (I2 I1 I0) Q0
Function
↑ 1 1 Increment by 2 Register
M
N
Clock

Use excitation table or equation

M N = 10 =>Load I2I1I0 to Q2Q1Q0:
Q(n) Q(n+1) D
<=> Qi (n+1) = Ii (n) ; i= {0,1,2}
0 0 0
Qi(n) Ii Qi(n+1) Di
0 1 1
1 0 0 0 0 0 0
1 1 1 0 1 1 1
1 0 0 0
M N = 00 => no change 1 1 1 1
<=> Qi (n+1) = Qi (n) ; i= {0,1,2}
=> Di = Ii (n) ; i= {0,1,2}
=> D2 = Q2 (n); D1 = Q0 (n); D0 = Q0 (n)
D2=I2; D1=I1; D0=I0
D2=Q2; D1=Q1; D0=Q0

MN= 01 =>Decrement by 3

Present State Next State D FF inputs

Q2 (n) Q1 (n) Q0 (n) Q2(n+1) Q1(n+1) Q0(n+1) D2 D1 D0
0 0 0 1 0 1 1 0 1
0 0 1 1 1 0 1 1 0
0 1 0 1 1 1 1 1 1
0 1 1 0 0 0 0 0 0
1 0 0 0 0 1 0 0 1
1 0 1 0 1 0 0 1 0
1 1 0 0 1 1 0 1 1
1 1 1 1 0 0 1 0 0

2
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

D0 = Q0’
D1:
Q1 Q0 00 01 11 10
Q2
0 0 1 0 1
1 0 1 0 1
D1 = Q1Q0’ + Q1’Q0 or D1 = Q1 ⊕ Q0

D2:
Q1 Q0 00 01 11 10
Q2
0 1 1 0 1
1 0 0 1 0

D2 = Q2’Q1’ + Q2Q1Q0 + Q2’Q0’

MN=11 =>Increment by 2

Present State Next State D FF inputs

Q2 (n) Q1 (n) Q0 (n) Q2(n+1) Q1(n+1) Q0(n+1) D2 D1 D0
0 0 0 0 1 0 0 1 0
0 0 1 0 1 1 0 1 1
0 1 0 1 0 0 1 0 0
0 1 1 1 0 1 1 0 1
1 0 0 1 1 0 1 1 0
1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0
1 1 1 0 0 1 0 0 1

D0 = Q0

D2:
Q1 Q0
00 01 11 10
Q2
0 0 0 1 1
1 1 1 0 0
D2= Q2Q1’ + Q2’Q1 or D2 = Q2 ⊕ Q1

D1:
Q1 Q0
00 01 11 10
Q2
0 1 1 0 0
1 1 1 0 0
D1=Q1’

3
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

4
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

Q0

or only Q’02
one
3-input
Q’1
gateQ0

Q’2
Q2

Q1

Q0
5
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

Question 3 (25 points)

Design a synchronous modulo-4 binary counter that has one control input W and that counts
forward or backward, as follows (assume an initial count value of 0):
• if W=0: counts backward by one (0
3
2
1
0…) at each clock pulse
• if W=1: counts forward by one (0
1
2
3
0…) at each clock pulse

a) Derive the state transition table and state diagram of the counter.

Transition table
W Q1(n) Q0(n) Q1(n+1) Q0(n+1) J1 K1 J0 K0
0 0 0 1 1 1 x 1 x
0 0 1 0 0 0 x x 1
0 1 0 0 1 x 1 1 x
0 1 1 1 0 x 0 x 1
1 0 0 0 1 0 x 1 x
1 0 1 1 0 1 x x 1
1 1 0 1 1 x 0 1 x
1 1 1 0 0 x 1 x 1

or
Transition table FF inputs #
Q1(n) Q0(n) W Q1(n+1) Q0(n+1) J1 K1 J0 K0
0 0 0 1 1 1 x 1 x
0 0 1 0 1 0 x 1 x
0 1 0 0 0 0 x x 1
0 1 1 1 0 1 x x 1
1 0 0 0 1 x 1 1 x
1 0 1 1 1 x 0 1 x
1 1 0 1 0 x 0 x 1
1 1 1 0 0 x 1 x 1

b) Design the sequential circuit by using JK flip flops and the required logic gates.
J1 :
Q1Q0W 00 01 11 10
Q1=0 1 0 1 0
Q1=1 X x x X
J1 = Q0’W’ + Q0W = or = (Q0 ⊕ W)’

6
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

K1:
Q1Q0W 00 01 11 10
Q1=0 X x x x
Q1=1 1 0 1 0
K1 = Q0’W’ + Q0W = or = (Q0 ⊕ W)’

The circuit is designed as follows

7
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

Question 4 (30 points)

A 3-bit arithmetic circuit takes three control bits, x, y and z, and two 3-bit data inputs, A and B.
The operations supported by the arithmetic unit are described in the following table.
Draw a detailed logic diagram of the circuit using 1-bit full adders and the digital components of
your choice (encoders, decoders, multiplexers, gates, etc.)
(Note: X’ is the 1’s complement of X)

xy z=0 z=1
00 F = A’ + 1 (2’s complement) F = A – 1 (decrement)
01 F = A – B (subtract) F = A – B + 1 (subtract with borrow)
10 F = A + 1 (increment) F = A (transfer)
11 F = A + B + 1 (add with carry) F = A + B (add)

z=0 z=1
xy FAA + FAB + Cy FAA + FAB + Cy
00 A’2A’1A’0+ 0 0 0 + 1 A2 A1 A0 + 1 1 1 + 0
01 A2 A1 A0 + B2’B1’B0’+ 1 A2 A1 A0 + (B2’B1’B0’+1)+1 0
10 A2 A1 A0 + 0 0 0 + 1 A2 A1 A0 + 0 0 0 + 0
11 A2 A1 A0 + B2 B1 B0 + 1 A2 A1 A0 B2 B1 B0 + 0

z=0 z=1
xy FAA + FAB + Cy FAA + FAB + Cy
00 A’2A’1A’0+ 0 0 0 + 1 A2 A1 A0 + 1 1 1 + 0
01 A2 A1 A0 + B2’B1’B0’+ 000 1 A2 A1 A0 + B2’B1’B0’+ 010 0
10 A2 A1 A0 + 0 0 0 + 1 A2 A1 A0 + 0 0 0 + 0
11 A2 A1 A0 + B2 B1 B0 + 1 A2 A1 A0 B2 B1 B0 + 0

8
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science
 CEG2136 Midterm Exam 2016

9
University of Ottawa, Faculty of Engineering, School of Electrical Engineering and Computer Science