SCHOOL OF ELECTRICAL ENGINEERING Answer all questions in

TOTAL
UNIVERSITI TEKNOLOGI MALAYSIA the provided spaces.
MARKS
SKEE 2263 DIGITAL SYSTEMS TEST 2 DATE: 10 JAN 2021
Name:

Lecturer: Section: UTM SPACE /100

Time: 60 minutes

Q1. A 4-bit Accumulator control input signal (Pr) performs functions as in Table Q.1. Design the
Accumulator by completing the circuit in Figure Q.1. Show the connections (between ADDER,
MUX and REGISTER), the inputs value and the primary inputs/output signals (Pr, clock, Z)
labels and all connection widths.
[30 marks]

Table Q.1
Pr Function

0 Z=Q-1

1 Z = Q+2

MUX 2:1 ADDER

REGISTER
I0 A

D Q

I1 B Cin
Sel

Figure Q.1
Q2. A machine produces a HIGH output when there has been exactly two consecutive 0’s followed
by two consecutive 1’s. Draw the state diagram for this machine using both Mealy and Moore
approaches. Example data input and corresponding output is shown below.

Input Y: 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 1
Output Z: 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0

Moore State Diagram:

Reset

S0

[15 marks]
Mealy State Diagram:
Reset

S0

[15 marks]
Q3. State diagram for a 3-bit counter is shown in Figure Q.3. The counter has input clock (CLK),
reset (RST) and 3-bit output (A2A1A0). Design this counter using design steps below.

Figure Q.3

a) From the state diagram, complete the state table in Table Q.3.
Table Q.3

Present State Next State FF Excitation

input
A2 A1 A0 A2+ A1+ A0+ D2 D1 D0
0 0 0
1
0 1 0
1
1 0 0
1
1 1 0
1

[20 marks]
b) Based on the state table (Table Q.3), implement the logic circuit of the counter. Use D flip-
flops and logic gates for the next state logic block.
[20 marks]