CONFIDENTIAL

FINAL EXAMINATION SEMESTER II

SESSION 2019/2020

COURSE CODE : SKEE 2263

COURSE : DIGITAL SYSTEMS

LECTURERS : DR. AMIRJAN BIN NAWABJAN

DR. ISMAHANI BINTI ISMAIL
DR. NORLINA BINTI PARAMAN
DR. ZULFAKAR BIN ASPAR
MR. ISMAIL BIN ARIFFIN
MR. IZAM BIN KAMISIAN
MRS. NORHAFIZAH BINTI RAMLI

PROGRAMME : SEEE / SEEL / SEEM / SKEE / SKEL / SKEM

SECTION : 01 / 02 / 03 / 04 / 05 / 06 / 07 / 08 / 09 / 10 / 11 / 12
/ 13

TIME : 2 HOURS 30 MINUTES

DATE : 08TH JULY 2020

INSTRUCTION TO CANDIDATE : ANSWER ALL QUESTIONS.

THIS EXAMINATION BOOKLET CONSISTS OF 10 PAGES INCLUDING THE FRONT COVER

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Q.1 Refer to the circuit in Fig. Q.1a.

(a) Fill in Table Q.1a. All numbers are 4 bits wide.
(10 marks)

Figure Q.1a

Table Q.1a

addsub A[3..0] B[3..0] X[3..0] Y[3..0] F[3..0]

0 0011 0101
1 0100 0110
0 0010 0111
1 0101 0001
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(b) Using one multi-bit adder, one 4:1 mux and a minimum number of logic gates,
design a combinational circuit that implements the functions listed in Table Q.1b.
The output F of the circuit is connected to a logic gate that generates a single bit
output Z, which is 1 when F is 0. All inputs, outputs and internal data paths, except Z,
are 4 bits wide.
(10 marks)

Table Q.1b

S1 S0 Function
0 0 F=B
0 1 F = One’s complement of A
1 X F = 2A
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Q.2 (a) Analyze the accumulator-based circuit in Figure Q.2a-i. The circuit performs
addition (A+B) when addsub = 0 and subtraction (A–B ) when addsub = 1. All bus
connectors are 4 bits wide. Complete the corresponding functional timing diagram
in Figure Q.2a-ii. All bus values (X and Q) are in hexadecimal.
(5 marks)

Figure Q.2a-i

Clk

X[3..0] 3 2 1 5 4

ldRa

ldRb

addsub

ldRd

Q[3..0] 0

Figure Q.2a-ii
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(b) A 10-bit counter module implements the functions listed in Table Q.2b-i.
(i) Determine the 10-bit register contents by completing Table Q.2b-ii.
(5 marks)
(ii) Implement the counter module using 2:1 multiplexers, registers and adders.
(10 marks)

Table Q.2b-i

Ld Ct Function RTL
0 0 Hold Q←Q
0 1 Count down Q←Q-1
1 X Load Q←D

Table Q.2b-ii

Clk Ld Ct D(hex) Q(hex)

0 1 0 355
1 1 1 002
2 0 0 256
3 0 1 333
4 0 1 001
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Q.3 A finite state machine circuit is given in Figure Q.3a-i and Q.3a-ii. Figure Q.3a-i shows the
next state logic and state register. Figure Q.3a-ii shows the output logic. The complete
circuit from Figure Q.3a-i is shown as a module labeled Next_State in Figure Q.3a-ii.
(a) Complete the waveform in Figure Q.3a-iii.
(5 marks)
(b) Generate the state table.
(5 marks)
(c) Sketch the state diagram.
(7 marks)
(d) Sketch the ASM equivalent of the state diagram.
(3 marks)

Figure Q.3a-i
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Figure Q.3a-ii

Figure Q.3a-iii
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Q.4 A Datapath Unit (DPU) of a greatest common divisor (GCD) finder is shown in Figure
Q.4a.
(a) Fill in the values for Zero, A<B, A and B columns in Table Q.4a by analyzing the
DPU upon receiving triggering clock pulses. The external values A_in = 36 and
B_in = 12 remain unchanged throughout the process.
(6 marks)

Go CU
Valid

selA LdA SelB LdB Zero A<B selC

DU

Zero? LT
comparator

out
A_in
0
A A
1
SUB
B_in 0
A-B
0 1
B
B
1

Figure Q.4a

Table Q.4a

A B
Clk selA ldA selB ldB selC Zero A<B (decimal) (decimal)

0 0 1 0 1 0 0 0 36 12
1 1 1 0 0 0
2 1 1 0 0 0
3 1 1 0 0 0
4 1 1 1 1 1
5 1 1 0 0 0
6 1 1 1 1 1
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(b) Based on the GCD datapath unit (DU) in Figure Q.4a and the high-level
(algorithmic) ASM chart in Figure Q.4b, derive low-level (control) ASM chart for
the CU.
(4 marks)
(c) Implement the GCD controller using one-hot encoding method. Draw the complete
circuit.
(10 marks)

Figure Q.4b
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Q.5 (a) The following set of decimal numbers need to be stored in fixed point representation.

0.1875, -2.5, -0.75, 3.0625

Find the Q number format that can represent all of the numbers exactly, i.e. with
zero error. Show your analysis.
(10 marks)
(b) Design an n-bit logic circuit that performs the function as shown in Table Q.5b. The
modules that are available for you to use are one n-bit PIPO register, one n-bit adder
(with Cin0 input available and the Coutn output disabled), one n-bit 2:1 mux, one n-
bit 4:1 mux and n-bit inverters as shown in Figure Q.5b. You can use multiple sets
of inverters.
(10 marks)

Table Q.5b

Y X RTL
0 0 Q←Q–1
0 1 Q ← (– Q)
1 0 Q←Q–P
1 1 Q←P–Q

Figure Q.5b
Q.1 (a) (10 marks)

Table Q.1a

addsub A[3..0] B[3..0] X[3..0] Y[3..0] F[3..0]

0 0011 0101 0011 0101
01010011

1 0100 0110 0100 1001 1110

0111
0 0010 0111 0010 0111 0010
1 0101 0001 0101 1110 0100

Q.1 (b) (10 marks)

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Q.2 (a) (5 marks)

Clk

X[3..0] 3 2 1 5 4

ldRa

ldRb

addsub

ldRd

Q[3..0] 0 6 C 6 6 0

Q.2 (b) (i) (5 marks)

Clk Ld Ct D(hex) Q(hex)

0 1 0 355 355
1 1 1 002 002
2 0 0 256 002
3 0 1 333 001
4 0 1 001 000

Q.2 (b) (ii) (10 marks)

 Q.3 (a) (5 marks)

Q.3 (b) (5 marks)

State Table
Present State Input Next State Output
S2 S1 S0 IN NS2 NS1 NS0 DONE WAIT
0 0 0 0 0 0 1 0 0
1 0 0 1
0 0 1 0 0 1 1 0 1
1 0 0 1
0 1 0 0 1 1 0 0 0
1 1 1 1
0 1 1 0 0 1 0 0 0
1 1 1 1
1 0 0 0 X X X X X
1
1 0 1 0 X X X X X
1
1 1 0 0 0 0 1 1 0
1 0 0 0
1 1 1 0 1 1 1 0 1
1 1 1 1
 Q.3 (c) (7 marks)

K-Map
S0 00 01 11 10 S0 00 01 11 10
IN IN
S2 S1 S2 S1
00 0 0 0 0 00 0 0 0 1
01 1 1 1 0 01 1 1 1 1
11 0 0 1 1 11 0 0 1 1
10 X X X X 10 X X X X

NS2 = *S2.S1.*S0 + S1.S0.IN + S1.S0 NS1 = *S2.S1.*S0 + S2.S0 +

S0.*IN

S0 00 01 11 10 S0 0 1
IN S2 S1
S2 S1
00 1 1 1 1 00 0, 0 0, 1
01 0 1 1 0 01 0, 0 0, 0
11 1 0 1 1 11 1, 0 0, 1
10 X X X X 10 X X

NS0 = S2.*IN + *S2.*S1 + S2.IN + S0.IN + DONE = S2.*S0, WAIT = S2.S0 + *S1.S0
S2.S0 (Rare answer)

Using Mux
Present State Input Next State Output
S2 S1 S0 IN NS2 NS1 NS0
SEL2 SEL1 SEL0 Mux2 Mux1 Mux0
0 0 0 0 0 0 1 0 0 1
1 0 0 1
0 0 1 0 0 1 1 0 *IN 1
1 0 0 1
0 1 0 0 1 1 0 1 1 IN
1 1 1 1
0 1 1 0 0 1 0 IN 1 IN
1 1 1 1
1 0 0 0 X X X X X X
1
1 0 1 0 X X X X X X
1
1 1 0 0 0 0 1 0 0 *IN
1 0 0 0
1 1 1 0 1 1 1 1 1 1
1 1 1 1
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Q.3 (d) (3 marks)
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Q.4 (a) (6 marks)

Table Q.4a

A B
Clk selA ldA selB ldB selC Zero A<B (decimal) (decimal)

0 0 1 0 1 0 0 0 35 10
1 1 1 0 0 0 0 0 25 10
2 1 1 0 0 0 0 0 15 10
3 1 1 0 0 0 0 1 5 10
4 1 1 1 1 1 0 0 10 5
5 1 1 0 0 0 0 0 5 5
6 1 1 1 1 1 1 0 5 0

Q.4 (b) (4 marks)

Reset

S0

0
Go
0
1

SelA, SelB 1
Go
LdA, LdB

S2
S1
VALID

1
zero

0
0 1
A<B

SelA, LdA
SelA, LdA SelB, LdB
SelC

Figure Q.4b
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Q.4 (c) (10 marks)

Next State Equation given Inputs: Go, Zero, A<B

𝑆0+ = 𝑆0. ̅̅
𝐺𝑜̅̅ + 𝑆2. ̅̅
𝐺𝑜̅̅

𝑆1+ = 𝑆0. 𝐺𝑜 + 𝑆1. 𝑧𝑒𝑟𝑜

̅̅̅̅̅̅.

𝑆2+ = 𝑆1. 𝑧𝑒𝑟𝑜 + 𝑆2. 𝐺𝑜

Mealy Outputs: Moore Output:

̅̅̅̅̅̅̅
𝑆𝑒𝑙𝐴 = 𝑆0. 𝐺𝑜 + 𝑆1. 𝑍𝑒𝑟𝑜. Valid = S2

𝐿𝑑𝐴 = 𝑆0. 𝐺𝑜 + 𝑆1. ̅̅̅̅̅̅̅

𝑍𝑒𝑟𝑜.

̅̅̅̅̅̅̅ (𝐴 < 𝐵)
𝑆𝑒𝑙𝐵 = 𝑆0. 𝐺𝑜 + 𝑆1. 𝑍𝑒𝑟𝑜.

𝐿𝑑𝐵 = 𝑆0. 𝐺𝑜 + 𝑆1. ̅̅̅̅̅̅̅

𝑍𝑒𝑟𝑜. (𝐴 < 𝐵)

̅̅̅̅̅̅̅ (𝐴 < 𝐵)
𝑆𝑒𝑙𝐶 = 𝑆1. 𝑍𝑒𝑟𝑜.
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Q.5 (a) (10 marks)

Data Q format
0.1875 0.0011 Q0.4
-2.5 101.1 Q2.1
-0.75 1.01 Q0.2
3.0625 011.0001 Q2.4
Answer Q2.4

Q.5 (b) (10 marks)

Figure Q.5b