Regulation: 2018

Reg. No.:

BANNARI AMMAN INSTITUTE OF TECHNOLOGY

(An Autonomous Institution Affiliated to Anna University, Chennai)
SATHYAMANGALAM – 638 401

END SEMESTER THEORY EXAMINATIONS - JANUARY 2022

III Semester

18IT302 & DIGITAL SYSTEM DESIGN

Degree & Branch: B.Tech. & IT

Time: 3 Hrs. Maximum: 100 Marks

Q. No. Questions

SECTION A COURSE OUTCOME 1 MAXIMUM: 20 MARKS

A1 Consider a conversation between a Human and a Human, between a Human and a computer. Human
can understand the language of anther human whereas Machine cannot understand the human
language. So it is essential to convert one form to another form. Based on this scenario solve the
following questions:

Fig.1 Basic Number Conversions

(i) The octal equivalent of 1100101.001010 is ________. (Can directly convert binary into octal
value). (3 Marks- [P/Ap,2])
(ii) The hexadecimal equivalent of the octal number 5401 is ________. (Convert octal to binary and
binary to hexadecimal). (3 Marks- [P/Ap,2])
(iii) Complement of the expression A’B + CD’ is _________. (2 Marks- [P/Ap,2])
(iv) The one input NAND and NOR gates behave like the basic operation of which of the logic gates?

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 (2 Marks- [P/An,2])
A2 The following Figures 2,3 depict the working of NAND and NOR gates in-case of two-way switch
scenario. The NAND gate performs the inversion operation on the AND gate, where it gives high output
(glowing of electric bulb) even if one of inputs is high or if none of the inputs is high. Similarly the NOR
gate depicted in Fig. 3 performs the inversion operation on the OR gate. It high output when both the
inputs are zero and produces low output in all other cases. Using the basic information about NAND
and NOR gates answer the questions given.

Fig.2 Working of NAND gate

Fig.3 Working of NOR gate

(i) a. Identify the output of the given logical diagram with three NOR gates in Fig 4:
(2 Marks-[P/An,2])

Fig .4 A logical circuit with three NOR gates

b. The obtained output is similar to the operation of a ________ gate. (2 Marks-[P/An,2])

(ii) Simplify the Boolean expression (x+y)(x+y’) (3 Marks-[P/Ap,2])

(iii) Consider the Boolean expression F=A’B+B’C+AC’. The term A’B is referred to as __________
and this form of representing the Boolean expression is referred to as ____________.
(3 Marks-[C/U,2])

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A3 The K-Map is used to simplify the Boolean expressions. Fig.5 depicts the representations of K-Map
with two, three and four variables. Answer the questions based on K-map.

Fig.5 Representations of two, three and four variable K-Map

(i) Simplify the given Boolean function using three-variable K-map (use the three variable K-map
format given in figure 5):
F(x, y, z)= ∑(0, 1, 2, 3, 5)
a. Write the minterms in truth table format
b. Plot it in K-map
c. Simplify and find the expression (6 Marks-[P/Ap,2])
(ii) Calculate the number of minterms with two 1’s in the function F(A,B,C,D) = ∑(0,2,3,6,7,8,10,12,13)
and write them too. (4 Marks-[P/An,2])
SECTION B COURSE OUTCOME 2 MAXIMUM : 20 MARKS
B1 A switching circuit has four inputs as shown in Fig.6. A and B represent the first and second bits of a
binary number N1.C and D represent the first and second bits of a binary number N2. The output is to
be 1 only if N1> N2.

N1

N2

Fig.6 A Switching circuit

(i) Write the minterm expansion for Y. (2marks - [Ap/P,2])

(ii) Write the correct logic expression for the minterm obtained in Question B1 (i).
(2marks- [Ap/P,2])
(iii) Draw the logical diagram for the switching circuit using the expression found in Question ii.
(2marks- [Ap/P,2])
(iv) The procedure for the design of the Combinational circuits are given. Fill out the missing step in
the procedure.

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 1. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
2. _____________.
3. Write down the switching expression(s) for the output(s).
4. Simplify the switching expression(s) for the output(s).
5. ______________
(4 Marks – [P/U,2])
B2 Thomson constructed the logic circuit to do addition and subtraction. Addition is having sum and carry
as outputs. Subtraction is having difference and borrow as outputs. The designed truth table and
system diagram is as follows

Fig.7.1 An Adder circuit Fig.7.2 A Subtractor circuit

ADDITION SUBTRACTION

X Y S C X Y D B

0 0 0 0 0 0 0 0

0 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

1 1 0 1 1 1 0 0

But the above design does not have a provision to carry over the carry and borrow. So he decided to
add the carry and Borrow along with the input. So the new adder and subtractor circuit is having 3 inputs
and 2 outputs.
(i) Obtain the Boolean expression for new adder and subtractor from truth table with 3 inputs and two
outputs (Using K-map). (6 marks -[P/Ap,3])
(ii) Draw the logical diagrams of the adder and subtractor circuits obtained in Question i.
(4 marks -[P/Ap,3])
B3 The example given in Fig.8 illustrates the process if encoding the input and sending it to the destination
end where the encoded input is decoded and original input is retrieved. This way the input can be
securely sent over the communication network. Based on this scenario answer the questions given
below:

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 Fig.8 Encoding and Decoding a message to improve the security in data transmission
(i) The truth table of a 4 to 2 Encoder is given:

Encoding is the task of converting data in one format to another format. Using the truth table of 4
to 2 Encoder obtain the conversion of an Octal to Binary Encoder (i.e. 8 to 3 Encoder).
(4 Marks - [P/Ap,2])
(ii) From the following options identify the type of Combinational circuit that is implemented using the
given code:

(3 Marks- [P/An,2])
(iii) Using the truth table given in Fig.9 of Binary to Gray code conversion identify the Boolean
expression of g0.

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 Fig.9 Binary to Gray code converter
(3 Marks – [P/Ap,2])
SECTION C COURSE OUTCOME 3 MAXIMUM: 20 MARKS
C1 ABC is an Eye hospital where a single doctor attends the patient. The Number of patients allowed for
visiting the Doctor during his visiting hours is 8 i.e. with token number 0 to 7. After the completion of 8
tokens counter is again reset to 0. Tokens are distributed based on the first come first serve basis. The
token order is incremented from 0 to 7 by 1. Fig.10 shows the Token display system in the ABC Hospital.

Fig.10 Token number display system in a Hospital

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 (i) The counter that would be suitable to display the token number to callout the patients in the ABC
Hospital is ____________.
(Pick the answer from the given list of options: A. Up counter B. Down Counter C. Up/Down
counter ) (2 Marks – [C/U,2])
(ii) The previous value of the Counter has to be stored in order to issue the next token to the patient
and also verify the total number of patients that would be attended by the Doctor in a day. The
token number is stored as the binary value in 3bits.The binary information stored in these elements
at any given time defines the __________ of the Counter circuit. (2 Marks – [C/U,2])
(iii) Draw the state diagram with three bit values to display the states of the Counter used for the
Hospital Management System. (3 Marks – [P/Ap,2])
(ii) If the Counter for Hospital token management is designed using an S-R latch with NOR gate with
inputs S, R and outputs Q and Q’ and demonstrate the condition that when there is no new patient
for visiting (i.e. both S and R is zero), the output will be the value stored in the memory.
(3 Marks – [P/Ap,2])
C2 A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle
GREEN is turned on for 70 seconds. YELLOW is turned on for 5 seconds and the RED is turned on
for 75 seconds. The traffic light has to be implemented using a finite state machine (FSM). The time
period of available clock is 5 seconds. Using this scenario answer the questions given. Fig.11 gives an
application of Finite state machine in Traffic signal controller.

Fig.11 Traffic signal controller(FSM)

(i) a. As shown in the Traffic signal controller which is a Finite State Machine, the state transition
happens ___________ in every clock cycle in an FSM.
b. In Traffic signal controller(FSM), the output is the function of both present state and the input.
This is an application of __________ type of FSM (4 Marks – [C/An,2])
(ii) The characteristic table of T flip-flop is given:

Using this characteristic table obtain the Excitation table and Characteristic equation of T flip-flop.
(4 Marks-[P/Ap,2])
(iii) Draw the logical diagram for the characteristic equation obtained. (2 Marks-[P/Ap,2])
C3 Registers are the memory elements that are used in sequential circuits to provide the feedback path.
The following figure.12 describes the scenario where registers are used to store and process one bit

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 binary information. The following figure resembles the movement of data in the registers. Using this
scenario answer the questions

Fig.12 Movement of data inputs in shift registers

(i) a. Observe the given diagram in Fig.13 and identify the type of circuit it belongs to.

Fig.13 Circuit diagram with Flip-flops

b. Identify the subcategory of the circuit to which the given circuit belongs to.
c. The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’
number of flip-flops is __________. (6 Marks-[P/U,2])
(ii) a. The HDL code for detecting the positive edge of the clock is _________.
b. The positive edge is the edge when the clock pulse moves from _______ level to ______
level. (4 Marks-[C/Ap,2])
SECTION D COURSE OUTCOME 4 MAXIMUM: 20 MARKS
D1 The asynchronous circuit is given in Fig 14. Observe the circuit and answer the questions given:

Fig.14 An Asynchronous sequential circuit

(i) Obtain the Boolean expression for Y1 and Y2 in Fig 14. (3 marks-[P/Ap,2])

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 (ii) Draw the K map for the Boolean expression of Y1 and Y2 obtained in i. (3 marks-[P/Ap,2])

Y1 Y2

(iii) Observe the given table and identify the condition that the circuit undergoes and give a two line
description.

(3 Marks-[C/U,2])
(iv) The memory elements in this circuit are _____________. (1 Mark-[C/U,2])
D2 A palace is designed with two doors X and Y to in and one door Z to out. The door in is treated as input
and door out is treated as output. A person enters through the door X has the possibility to visit again
through the door Y but the person cannot again go through the door X. The palace is designed in the
asynchronous sequential circuit manner. Whenever the person entered through the door Y (i.e. y=1).
The output of the door Z will be followed by the input X. Suppose no person entered(Y=0) the input that
was present at the X at a time will retained as the output Z. Design the asynchronous circuit for the
palace. Given the state table for the palace design. Use the state table and answer the questions given:

(i) From the given State table form the Primitive Flow table.
AB 00 01 11 10

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 e

f
(6 Marks-[P/Ap,2])
(ii) Obtain the Reduced Flow table and Flow table from the Primitive Flow table obtained in
Question. D1 (i).
(4 Marks-[P/Ap,2])
D3 Latches are basic storage elements that operate with signal levels (rather than signal transitions).
Latches controlled by a clock transition are flip-flops. Latches are level-sensitive devices. Latches are
useful for the design of the asynchronous sequential circuit. As latch is single bit storage element, they
may be used as storage device in power gating circuits and clock. Latches may get into a Race condition
when the when more than 1bit state value changes simultaneously. The states given adjacent
assignments should have only one-bit change at a time. So a Race-free state assignment has to be
given to the circuits in order to make the circuit a stable one. Using this information answer the questions.
(i) Observe the given figure.15 and verify whether it has a Race-free state assignment or not and
support your answer with a two line description.

Fig.15 State diagram of a circuit (4 Marks-[P/An,3])

(ii) Shared row method and Multiple row method are the two methods followed to provide a Race-
free state assignment. Shared row method performs a Race-free assignment by adding an extra
row to the flow table. Multiple row method adds extra binary variables to the table so that the
adjacency property is satisfied and a Race-free state assignment could be obtained.

Based on the description of the methods given, which one would be better when it comes to a
Race-free assignment? (2 Marks-[P/An,2])
(iii) a. Hazards are the spike or glitch or unwanted transients that may occur in the output of the
circuit. The main cause of hazards is difference in propagation delays at different paths. So
out of the three kinds of circuits (Combinational, Synchronous sequential and Asynchronous
sequential circuits) the one that does not face any problem due to hazards is
______________.
b. State the reason for the same. (4 Marks-[P/An,3])
SECTION E COURSE OUTCOME 5 MAXIMUM: 20 MARKS
E1 A programmable logic device (PLD) is an electronic component that is used to
build reconfigurable digital circuits. Unlike integrated circuits (IC) which consist of logic gates and have
a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be
used in a circuit it must be programmed (reconfigured) by using a specialized program. The following
figures 16.1&16.2 show the types of memory and their applications. Use these examples and answer
the questions given.

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 Fig.16.1 Applications of ROM

Fig.16.2 Applications of RAM

(i) From the given figures identify the types of PLD (Programmable Logic Device):

Fill the empty boxes 1,2,3,4 with appropriate terms to obtain the block diagram of PLA and PAL.
List of terms:
a. Programmable OR Array
b. Fixed OR Array
c. Programmable AND Array
d. Fixed AND Array (4 Marks-[C/U,1])

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 (ii) The PLD looks like a black box consisting of programmable switches and logic gates. The main
function of the ___________ is to let the logic gates within the PLD to be associated mutually to
execute logic circuits. (2 Marks-[C/U,2])
(ii) The memory that stores the binary information in the form of electric charges on capacitors
provided inside the chip by MOS transistors. The stored charge on the capacitors tends to
discharge with time and the capacitors must be recharged by refreshing the memory. This kind of
memory is called __________ and it is ___________. (4 Marks-[P/U,2])
E2 PLAs could be used as counters in real life applications. In our household appliances, for both microwave
oven and washing machine, we set the device to particular time, and it starts decreasing for every
second. When the value of counter becomes zero, it activates the switch ON / OFF. This, the operation
of the device is controlled by counters. Use this scenario and answer the questions given. PLAs are used
in counters, decoders etc. Using this scenario and Fig.17 answer the questions given.

Fig.17 Application of counters in Microwave ovens

(i) a. The type of PLD that is used to program basic logic functions is ___________.
b. The difference between PLA and PAL is _____________. (4 Marks-[C/U,2])
(ii) The Boolean expressions for the functions F1(A,B,C)=∑m(1,3,6,7) and F2(A,B,C)= ∑m(0,2,4,5)
is __________. (6 Marks-[C/U,2])
E3 The term FPGA stands for Field Programmable Gate Array and, it is a one type of semiconductor logic
chip which can be programmed to become almost any kind of system or digital circuit, similar to PLDs.
The applications of FPGA include Medical Electronics, Wireless communications, Aerospace and
Defense, Video and Image processing, Security systems, Consumer Electronics, Distributed Monetary
Systems, Scientific instruments etc. Fig.18 illustrates the use of FPGAs in Video processing. Using
these applications answer the questions given.

Fig.18 Application of FPGA in video processing

(i) a. Many companies are transitioning to using FPGAs for their processor designs instead of ASICs.
The reason for this transition is ___________.
b. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
c. The logic cells in FPGA are made up of single NAND logic gate. Say True/False.
(6 Marks-[P/Ap,2])

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(ii) a. The FPGA architecture for the given scenario like video games is specified using a language
known as ___________ .
b. It is similar to the one used for an ___________. (4 Marks-[C/An,2])
***End of Question Paper***

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