ICT121

Examination – January Semester 2018

Introduction to Computer Systems

Architecture
Wednesday, 16 May 2018 1:00pm – 3:00pm

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Time allowed: 2 hours

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INSTRUCTIONS TO STUDENTS:

1. This examination contains FOUR (4) questions and comprises NINE (9)
printed pages (including cover page).

2. You must answer ALL questions.

3. All answers must be written in the answer book.

4. This is a closed-book examination.

5. Calculators are NOT allowed in this examination.

6. T121 instruction set summary (Appendix 1) and a partial ASCII codes table
(Appendix 2) are attached.

At the end of the examination

Please ensure that you have written your examination number on each answer book
used.

Failure to do so will mean that your work cannot be identified.

If you have used more than one answer book, please tie them together with the string
provided.

THE UNIVERSITY RESERVES THE RIGHT NOT TO MARK YOUR

SCRIPT IF YOU FAIL TO FOLLOW THESE INSTRUCTIONS.

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Examination – January Semester 2018
Answer all questions. (Total 100 marks)

Question 1

A microprocessor uses 8-bit for integer representation and 32-bit for floating point
number representation. Analyse the various number representations and answer the
following questions.

(a) Given A = 5410 and B = 3810.

(i) Give the ASCII character represented by B if its value is 3810.

(2 marks)

(ii) Express the value of A and the value of B in 8-bit sign-magnitude

representation.
(2 marks)

(iii) Show how the processor computes the arithmetic operation B – A by

performing the computation in 2’s complement arithmetic. Convert the
result to decimal and show it is equal to -16.
(6 marks)

(iv) Show how the processor computes the logic operation

(NOT(A) AND B) OR (NOT(B) AND A). Express the result in
hexadecimal.
(6 marks)

(v) Examine the values of A, B and the result of the operation in (iv).
Explain and deduce the logic operation equivalent to the logic operation
(NOT(A) AND B) OR (NOT(B) AND A).
(3 marks)

(b) This microprocessor uses the specifications shown in Figure Q1(b) for 32-bit
floating point number representation. If the representation in hexadecimal
number is C1E0 0000, determine the decimal value of the representation.
(6 marks)

Bit 31 30 23 22 0
1 8 bits 23 bits

Sign Exponent (E) is an Mantissa (M) is an unsigned

0: positive unsigned integer fixed point fraction
1: negative
Decimal value = <sign> (1.M) * 2E-127

Figure Q1(b)

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Examination – January Semester 2018
Question 2

Figure Q2 shows the characteristics of a hypothetical processor, relevant portions of

memory, processor registers and some I/O devices. For the instruction format shown in
Figure Q2(i), if it is an I/O instruction, bits 4 to 15 identifies a particular I/O device,
else bits 4 to 15 identifies a memory address.

Bit 0 3 4 15
Opcode Memory address or I/O device number

(i) Instruction format

Bit 0 1 15
Sign Magnitude

(ii) Integer format

Program counter (PC) = Address of instruction

Accumulator (AC) = Temporary storage
Instruction register (IR) = Instruction being executed
(iii) Internal CPU registers

0001 = Load AC from memory

0010 = Store AC to memory
0011= Add to AC from memory
0100 = Subtract contents of memory from AC
0101 = Load AC from I/O
0110 = Store AC to I/O

(iv) Partial list of opcodes

Memory CPU registers

700 5009 700 PC
701 4900 AC
702 2901 IR

900 0002 I/O Devices

901 Dev 8
0008 Dev 9
(All numbers are in hexadecimal)

(v) Contents of memory, registers and I/O devices at start of program

Figure Q2

(a) Examine Figure Q2 and determine the number of memory locations this
processor can address.
(2 marks)

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Examination – January Semester 2018
(b) For the instruction format shown in Figure Q2(i), if the operand is a memory
address, indicate the addressing mode used.
(2 marks)

(c) This hypothetical processor is to execute the following program:

1. Load AC from device 9.

2. Subtract contents of memory location 900 from AC.
3. Store AC to memory location 901.

There are 6 steps consisting of 3 pairs of a fetch and execute cycles. For each
step, describe what happens and list the contents of the following registers:

(i) PC at the start of each cycle,

(ii) AC at the end of each cycle and
(iii) IR at the end of each cycle.

Assume the initial values are as given in Figure Q2(v). Tabulate your answer
using the format given in Table Q2(c).

Step PC at start of cycle AC at end of cycle IR at end of cycle

1 700 Empty 5009
Fetch Description: The contents at address 700 is loaded to register IR.
PC is incremented by 1.
2 ? ? ?
Execute Description

3 ? ? ?
Fetch Description

4 ? ? ?
Execute Description

... ... ... ...

Table Q2(c)
(15 marks)

(d) Explain the TWO (2) approaches to deal with multiple interrupts.
(6 marks)

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Examination – January Semester 2018
Question 3

This question is based on the EASY68K simulated processor. Use the T121 Processor
Instruction Set of the EASY68K simulator to answer the following questions.

(a) Figure Q3(a) shows the contents of a memory segment and a program.

address contents ORG $002000

(I) START MOVE.L #$5000, A0
005000 66 (II) MOVE.W #$ABCD, (A0)+
005001 77 (III) MOVE.W (A0), D0
005002 88 (IV) MOVE.L $5000, D1
005003 99 STOP #$2700
END START

Figure Q3(a)

Assume the contents of registers A0, D0 and D1 are set to 00000000 before the
execution of the program. All numbers are in hexadecimal.

(i) What will be the contents of the memory segment shown in Figure Q3(a)
after the execution of the program?
(6 marks)

(ii) What will be the contents of registers A0, D0 and D1 after the execution
of the program?
(3 marks)

(iii) Identify the addressing mode used in each of the instructions from (I) to
(IV).
(4 marks)

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Examination – January Semester 2018
(b) Figure Q3(b) shows the structure of an incomplete program based on the
course’s simulated processor. The program has a subroutine labelled, SUBR.
Assume the contents of all data and address registers are equal to zero before
the start of the program. All numbers are in hexadecimal.

ORG $1000
START <insert your codes (I) here>
. . .
STOP #$2700
SUBR MOVE.B $300, D0
AND.B $301, D0
MOVE.B D0, $400
RTS
ORG <insert your codes (II) here>
. . .
END START

Figure Q3(b)

(i) What is the function of the subroutine? Do not give a description on an

instruction-by-instruction level; give the overall task of the subroutine.
(2 marks)

(ii) Write the codes, (I) and (II), to develop the program to call the
subroutine and create some test values to test its functionality. The
subroutine occupies memory space just below the main program.
Initialise test data: 1, 2, 3… up to the required number deduced in part
(b)(i).
(6 marks)

(iii) Demonstrate TWO (2) advantages of using subroutines.

(4 marks)

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Examination – January Semester 2018
Question 4

Figure Q4 shows the internal architecture of a computer system.

Primary Secondary
storage storage

System Bus
I/O unit

CPU

Figure Q4

(a) Draw the internal architecture of the CPU and describe the THREE (3) most
important components in it.
(6 marks)

(b) Primary storage can be classified as volatile and non-volatile types of memory.
Summarise the features of each type.
(4 marks)

(c) Describe the purpose of Secondary storage.

(2 marks)

(d) State TWO (2) major functions of the I/O unit. Summarise how data buffering
improves the performance of the I/O unit.
(6 marks)

(e) Describe the interaction of the CPU, stack memory and the I/O unit when an
interrupt is generated by an external device.
(7 marks)

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Examination – January Semester 2018
 Appendix 1 T121 Processor Instruction Set Summary
Operation NZ BWL Description Remarks
Move
MOVE <EA1>,<EA2> ** XXX move data

Arithmetic
ADD <EA1>, An or Dn ** XXX add binary
SUB <EA1>, An or Dn ** XXX subtract binary

Logical
AND <EA3>, Dn ** XXX logical AND
NOP <EA3>, Dn -- no operation
OR <EA3>, Dn ** XXX logical OR
NOT Dn ** XXX logical NOT

Control
BRA <Label> -- branch always
BSR <Label> -- branch subroutine
BNE <Label> -* branch not equal
BMI <Label> *- branch on negative
BPL <Label> *- branch on positive
JMP <Label> -- jump always
RTS -- return from subroutine
STOP #$2700 stop
- flag not affected , * flag affected
<EA1> = Dn, An, (An), (An)+, $<data>, #$<data>
<EA2> = same as <EA1> except #$<data>
<EA3> = Dn, #<data>

An: Address register A0 to A7

Dn: Data register D0 to D7
(An) : Content of address whose address is in An
(An)+: Similar to (An) but after instruction An=An+1 for.B, An+2 for .W and An+4 for .L
$nnnn: 16-bit Hexadecimal address
$nnnnnnnn: 32-bit Hexadecimal address
#$nn: 8-bit immediate Hexadecimal data
#$nnnn: 16-bit immediate Hexadecimal data
#$nnnnnnnn: 32-bit immediate Hexadecimal data

T121 Stack operation

MOVE.L Dn,-(A7)
- Push operation: Dn data store on the stack. A7-4 =A7 after operation
MOVE.L (A7)+,Dn
Pop operation: Stack data is put back to Dn. A7+4 =A7 after operation

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Examination – January Semester 2018
 Appendix 2 Partial ASCII Table

Char Binary Hex Char Binary Hex Char Binary Hex

00100000 20 A 01000001 41 a 01100001 61
! 00100001 21 B 01000010 42 b 01100010 62
" 00100010 22 C 01000011 43 c 01100011 63
# 00100011 23 D 01000100 44 d 01100100 64
$ 00100100 24 E 01000101 45 e 01100101 65
% 00100101 25 F 01000110 46 f 01100110 66
& 00100110 26 G 01000111 47 g 01100111 67
‘ 00100111 27 H 01001000 48 h 01101000 68
( 00101000 28 I 01001001 49 i 01101001 69
) 00101001 29 J 01001010 4A j 01101010 6A
* 00101010 2A K 01001011 4B k 01101011 6B
+ 00101011 2B L 01001100 4C l 01101100 6C
, 00101100 2C M 01001101 4D m 01101101 6D
- 00101101 2D N 01001110 4E n 01101110 6E
. 00101110 2E O 01001111 4F o 01101111 6F
/ 00101111 2F P 01010000 50 p 01110000 70
0 00110000 30 Q 01010001 51 q 01110001 71
1 00110001 31 R 01010010 52 r 01110010 72
2 00110010 32 S 01010011 53 s 01110011 73
3 00110011 33 T 01010100 54 t 01110100 74
4 00110100 34 U 01010101 55 u 01110101 75
5 00110101 35 V 01010110 56 v 01110110 76
6 00110110 36 W 01010111 57 w 01110111 77
7 00110111 37 X 01011000 58 x 01111000 78
8 00111000 38 Y 01011001 59 y 01111001 79
9 00111001 39 Z 01011010 5A z 01111010 7A

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Examination – January Semester 2018