CONFIDENTIAL

FINAL EXAMINATION SEMESTER 2

SESSION 2017/2018

COURSE CODE : SKEE 2263

COURSE NAME : DIGITAL SYSTEMS

LECTURERS : DR ISMAHANI BINTI ISMAIL

DR NORLINA BINTI PARAMAN
DR ZULFAKAR BIN ASPAR
ABDUL HAMID BIN AHMAD
ISMAIL BIN ARIFFIN
IZAM BIN KAMISIAN
KAMAL BIN KHALIL
MUHAMMAD MUN’IM BIN AHMAD ZABIDI
NORHAFIZAH BINTI RAMLI

PROGRAMME : SKEE/SKEL/SKEM

SECTIONS : 01-10

TIME : 2 HOURS 30 MINUTES

DATE : 2nd JUNE 2018

INSTRUCTION TO Part A: answer 2 out of 3 questions.

CANDIDATES Part B: answer 2 out of 3 questions.
Part C: answer 1 out of 2 questions.

THIS EXAMINATION BOOKLET CONSISTS OF 14 PAGES INCLUDING THE FRONT

COVER.
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Part A (Answer 2 out of 3 questions)

Q.1 (a) Analyze the circuit in Figure Q.1(a)-i and the corresponding timing diagram in
Figure Q1(a)-ii. The carry in and carry out of the adder are not used. Complete the
timing diagram by filling in the values for Q[3..0] in hexadecimal and drawing the
waveform for Z. Write your answer by filling out Figure Q.1(a)-ii in page 12. Detach
and submit page 12 together with your answer booklet.
(10 marks)

Figure Q.1(a)-i.

Figure Q.1(a)-ii.

(b) Implement the function Z =2X - Y using 24× 4 ROM as shown in Figure Q.1(b).
X[1:0] and Y[1:0] are unsigned 2-bit numbers. Z[3:0] is in two’s complement
format. Write the content at each memory location in binary for the ROM.
(10 marks)

Figure Q.1(b).
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Q.2 (a) Consider the universal shift register with control signal S[1:0] in Figure
Q.2(a)-i. Complete the corresponding timing diagram in Figure Q.2(a)-ii.
Write your answer by filling out Figure Q.2(a)-ii in page 12. Detach and
submit page 12 together with your answer booklet.
(10 marks)

Figure Q.2(a)-i.

Figure Q.2(a)-ii.

(b) Design a multiplier circuit to calculate the product of two 3-bit numbers,
P = A × B.

(i) Show the steps of multiplying the two 3-bit binary numbers,
identified as A = {a2a1a0} and B= {b2 b1 b0}.
(3 marks)
(ii) Draw the circuit that implements the 3 × 3 multiplication function.
Use AND gates, half adder and full adder. Do not draw the internal
circuit of half adders and full adders.
(7 marks)
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Q.3 (a) Find the critical path delay for the circuit in Figure Q3(a)-i by filling table
Q.3(a)-i.
(10 marks)

Figure Q.3(a)-i.

Table Q.3(a)-i.
Path Delay (ns)

The critical path delay is

(b) Figure Q3(b)-i shows the top level diagram for a 4-bit sorter which outputs the
smaller of its two inputs, X and Y, on the first output, min(X,Y), and the larger
input on the second output, max(X,Y). The partial design of the sorter using
one 4-bit comparator and two 4-bit 2:1 multiplexers is given in Figure Q3(b)-
ii. Complete the design by showing the wiring between the comparator and
multiplexers. Label all inputs and outputs. Write you answer by filling the
boxes in Figure Q.3(b)-ii given in page 13. Detach and submit page 13 together
with your answer booklet.
(10 marks)

Figure Q3(b)-i.

Figure Q3(b)-ii.
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Part B (Answer 2 out of 3 questions.)

Q.4 (a) The FSM circuit shown in Figure Q.4(a)-i has two inputs X1, X2 and two
outputs Z1, Z2. The contents of the ROM are given in Table Q4(a)-i. Assume
QB is MSB.
(i) Use K-Map to find the simplest expression for Z1 and Z2 and determine
the type of FSM circuit employed.
(ii) Construct the state diagram.
(ii) Find the sequence of output Z1Z2 generated when given input sequence
X1X2 = 00,10, 01, 11, 01
(10 marks)

Figure Q.4(a)-i.

Table Q.4(a)-i.
A3 A2 A1 A0 D3 D2 D1 D0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 1 0
0 0 1 1 0 1 1 0
0 1 0 0 1 1 0 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 1
1 0 0 0 1 1 0 0
1 0 0 1 0 0 0 0
1 0 1 0 1 1 0 1
1 0 1 1 0 0 0 1
1 1 0 0 1 0 0 0
1 1 0 1 0 1 0 0
1 1 1 0 1 0 0 0
1 1 1 1 0 1 0 0
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(b) A state diagram with two inputs a and b, and an output Y is shown in Figure
Q.4(b)-i. Draw the corresponding circuit using DFFs.
(10 marks)

Figure Q.4(b)-i.

Q.5 Figure Q.5 shows a finite string recognizer with one input (X) and one output (Z).
(a) (i) Determine the sequence of output (Z) by completing the relationship
between input and output below.

X : 011011110111100111
Z : ..................
(2 marks)
(ii) State the bit sequences that will be recognized.
(4 marks)
(b) Design the FSM by using D flip-flops and binary encoding technique.
(14 marks)

Figure Q.5.
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Q.6 (a) Festive lights has become a must in enlivening any celebration in the world.
A festive lights has Green (G), Yellow (Y), Red (R), Blue (B) and Amber (A)
lights where the green light turns on for 9 clock cycle, yellow light turns on
for 3 clock cycle, red light turns on for 6 clock cycle, blue light turns on for 3
clock cycle and amber light turn on for 3 clock cycle. The festive light turn on
in G → Y → R → B → A sequence repeatedly. By using the datapath unit
(DU) as shown in Figure Q.6(a), sketch the state diagram for the control unit
(CU) for the festive lights. Use Moore model for the CU.
(10 marks)

Figure Q.6(a).

(b) Referring to Figure Q.6(a), if R output is not used and the state diagram for
the CU is as shown in Figure Q.6(b)-i, draw the timing diagram for output G,
A, B and Y for 13 clock cycles after Reset has been asserted. Write your
answer by filling the boxes in Figure Q.6(b)-ii given in page 13. Detach and
submit page 13 together with your answer booklet.
(10 marks)

Clock

Reset
1

G
0

A
0

B
0

Y
0

Figure Q.6(b)-i. Figure Q.6(b)-ii.

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Part C (Answer 1 out of 2 questions)

Q7. A ones counter is a circuit which receives an input word, counts the number of one
(1) bits in the input word, and outputs the ones count. For example, if the input bit
contains 1111 0000, the output is 0100 because there are four ones in the input. Figure
Q.7-i shows the datapath-unit (DU) and the control-unit (CU) for an n-bit ones
counter. Clock signals are not shown. Both CU and DU are triggered by the same
clock edge. Table Q.7-i defines the inputs, the outputs and the control signals used in
the ones counter.

Figure Q.7-i: CU+DU for a ones counter.

Table Q7-i: Function of input, output and control signals in a ones counter. The data input is
assumed to be 8 bits wide.

Table Q7-i.
CU
Input Output
st Start bit counting operation done Bit counting complete
Interface
CU to DU DU to CU
Loads shift register A and
load zero Register A contains all zeroes
clears counter B
Shifts the contents of
en_sh a0 Bit 0 of register A
register A right
en_ct Increments counter B by 1
DU
Input Output
data 8-bit data input count 4-bit result
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Figure Q.7-ii: Low level ASM Chart for ones counter.

(a) The low level ASM Chart for ones bit counter is shown in Figure Q.7-ii. Based
on the given CU+DU and ASM of the bit counter, fill in the timing diagram in
Figure Q.7-iii. Register values are in binary. Fill out the duplicate table in Page
14 and attach it to the answer booklet.
(8 marks)
(b) Based on the CU's ASM chart in Figure Q.7-ii, design and implement the control
unit using one-hot state assignment encoding method.
(12 marks)

Figure Q.7-iii: Timing diagram for ones counter

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Q8. A Datapath Unit is given in Figure Q.8-i while the flowchart of the operations is shown in
Figure Q.8-ii. The circuit finds the Greatest Common Denominator (GCD) of two inputs,
Ain and Bin. The width of the data lines is 8 bits. Clock signals are not shown. Both CU
and DU are triggered by the same clock edge. Table Q.8-i defines the inputs, the outputs
and the control signals used in the GCD circuit.

Control Unit (CU)

st done
selA enA selB enB zero lt

GCD
B=0? A<B
Ain 0
1
A
2 sub

0
B
Bin 1

Datapath Unit (DU)

Figure Q.8-i: CU+DU for greatest common denominator (GCD) circuit.

Table Q.8-i.
CU
Input Output
st Start operation done Operation complete
Interface
CU to DU DU to CU
selA Select source of data to register A zero Register B contains 0
enA Enables loading of register A Contents of register A is
lt
selB Selects source of data into register B less than register B (A<B)
enB Enables loading of register B
DU
Input Output
Ain 8-bit data input to register A GCD 8-bit result
Bin 8-bit data input to register B
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Figure Q.8-ii: Low level ASM Chart greatest common denominator (GCD) circuit.

(a) The low level ASM Chart for greatest common denominator (GCD) circuit is shown
in Figure Q.8-ii. Based on the given CU+DU and ASM, fill in the timing diagram in
Figure Q.8-iii. Register values are in decimal. Fill out the duplicate table in Page 14
and attach it to the answer booklet
(8 marks)
(b) Based on the CU's ASM chart in Figure Q.8-2, design and implement the control unit
using one-hot state assignment encoding method.
(12 marks)

Figure Q.8-iii: Timing diagram for greatest common denominator (GCD) circuit.
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Tear-Out Answer Forms.

Name: …………………………………………..
Section: …………………………………………

Q1.

Figure Q.1(a)-ii.

Q2.

Figure Q.2(a)-ii.
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Name: …………………………………………..
Section: …………………………………………

Q3.

Figure Q3(b)-ii.

Q6.

Figure Q.6(b)-ii.
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Name: …………………………………………..
Section: …………………………………………

Q7.

Figure Q.7-iii.

Q8.

Figure Q.8-iii