Indian Institute of Technology (IIT) – BHU

Department of Electronics Engg., End Term Assignment, 2021-22

EO-301, DIGITAL CIRCUITS AND SYSTEMS

Duration: 1 day Max. Marks: 25

Note: 1. Answer all questions only in the sequence given in the question paper. Any deviation
from the sequence will lead to loss of marks for the questions which are out of place. 2. Step
marking is there so stepwise solution should be written properly. All the questions are
compulsory, 3. The symbols have their usual meaning. 4. If any question appears to be
ambiguous, use your own interpretation with suitable justification. Each question carries 4
marks

****A single PDF file should be submitted solving all the questions sequentially. All questions
should be solved step by step with explanation for all the critical steps for step marking.
Direct answers without intermediate steps will lead to reduction of marks. ****

Qus 1) (a) Fig 1 shown is a NAND implementation of gated D-latch:

Fig.1
The timing diagrams of D and C are shown in Fig.2. Draw the timing diagram for Q
and T: (Assume that Q=1 and T=0 at t0 and there is no gate delay).

Fig.2
(b) Inputs to the J-K flip flop and clock pulse are given in Fig. 3. Flip flop is operating at
negative edge trigger of the clock pulse applied to it.
(i) Sketch the output Q of the J-K flip flop. Assume that the initial output of the flip flop is at
logic 1 and there is no gate delay.
(ii) Draw the excitation table for J-K flip flop.

Fig.3

Qus 2) The circuit shown in Fig.4 below shows a sequential circuit using D Flip Flops, and
Multiplexers. Assuming that A1, A0, and S are the inputs of the circuit, and Q1 is 0, Q 0 is 1 when
time equals 0 (t0), show the timing diagram for Q 1 and Q 0 .

Fig.4

Qus 3) Fig 5 represent a multiplier circuit that takes two-bit binary numbers X1X0 and Y1Y0
and produces an output binary number Z3Z2Z1Z0 that is equal to the arithmetic product of the two
numbers. Design the logic circuit for the multiplier.
 Fig 5
Qus 4) Design a counter which simultaneously satisfies all of the following requirements:
(i) Have no input signal.
(i) Have two-bit output signals called Y1 and Y0. Y1 is the MSB.
(iii) The counting sequence agrees with the following state diagram:

Fig.6
(iv) Use exactly one D flip-flop and one J-K flip-flop.
(v) The counter output Y0 is the output of the J-K flip-flop.
(vi) The counter output Y1 is the output of the D flip-flop.
(vii) No additional gate allowed.

Qus 5) Design a state machine which simultaneously satisfies all of the following requirements:
(i) Have one-bit input signal called W.
(ii) Have four-bit output signals called Y3 Y2 Y1 and Y0. Y3 is the MSB.
(iii) The counting sequence agrees with the following state diagram:

Fig 7
The numbers on the arrows indicate the values of W.
(iv) The output is simply the unsigned binary representation of the state in the state transition
diagram.
(v) Use exactly one D flip-flop.
(vi) Additional AND, OR, NOT gates are allowed.

Qus 6) Design a state machine which simultaneously satisfies all of the following
requirements:
(i) Have one-bit input signal called W.
(ii) Have one-bit output signal called Y.
(iii) The counting sequence agrees with the following state diagram:
 Fig.8
(iv) The output is simply the unsigned binary representation of the state in the state transition
diagram.
The numbers on the arrows indicate the values of W.
(v) Use exactly one D flip-flop.
(vi) Additional AND, OR, NOT gates are allowed.

------x---------
 Indian Institute of Technology (IIT) – BHU
Department of Electronics Engg., Post mid and end term quizes, 2021-22

EO-301, DIGITAL CIRCUITS AND SYSTEMS

Duration: 1 day Max. Marks: 25

Note: 1. Answer all questions only in the sequence given in the question paper. Any deviation
from the sequence will lead to loss of marks for the questions which are out of place. 2. Step
marking is there so stepwise solution should be written properly. All the questions are
compulsory, 3. The symbols have their usual meaning. 4. If any question appears to be
ambiguous, use your own interpretation with suitable justification.

****A single PDF file should be submitted solving all the questions sequentially. All questions
should be solved step by step with explanation for all the critical steps for step marking.
Direct answers without intermediate steps will lead to reduction of marks. ****

Table 1 Marks Distribution

Question Number Marks

1 6

2 6

3 4

4 3

5 6

Q1. Design a circuit that will function as prescribed by the state diagram shown in figure
using following flip-flop according to least significant decimal digits of your roll number:
(i) Roll no. 1 to 20, SR flip-flop.
(ii) Roll no. 21 to 40, JK flip-flop.
(iii) Roll no. 41 to 60, T flip-flop.
(iv) Roll no. 61 to end, D flip-flop.
Q2. Design one Mealy sequence detector sequence detector, detecting a binary sequence of
least significant 3 bits of last decimal digit of your roll number. Use the flip flop also
according to least significant 2 decimal digits of your roll number.
(i) Roll no. 1 to 20, JR flip-flop.
(ii) Roll no. 21 to 40, SR flip-flop.
(iii) Roll no. 41 to 60, D flip-flop.
(iv) Roll no. from 61 to end, T flip-flop.
For example, if your roll number has least significant decimal digit of 9, then its BCD equivalent
is 1001, so you should design for detecting 001 sequence. Further, for example, if your roll
number has least significant decimal digit of 0, then its BCD equivalent is 0000, so you should
design for detecting 000 sequence.

Q3. Convert D flip-flop into: (a) SR flip-flop (b) JK flip-flop. Also describes the steps.
Q4. What is a universal shift register? Draw the diagram and explain the function of each
input and output with example.

Q5. Design the sequential circuit specified by the state diagram of fig shown below by using
following flip-flop according to least significant 2 digits of your roll number:
(i) Roll no. 1 to 20 T flip-flop
(ii) Roll no. 21 to 40 D flip-flop.
(iii) Roll no. 41 to 60 JK flip-flop.
(iv) Roll no. 61 and above SR flip-flop.
------x---------