U.S.N.

BMS College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

December 2017 Semester End Main Examinations

Course: Digital Electronics Duration: 3 hrs
Course Code: 15ES3GCDEC Max Marks: 100
Date: 19.12.2017

Instructions: Answer 5 full questions choosing one full question from each unit

UNIT 1
1 a In the circuit shown in figure 1a, S 2 to S0 are select lines and X7 to X0 are input 5
lines. S0 and X0 are LSBs. Analyze the circuit and find the output Y.

Fig. 1a
b Implement the following function f1(x,y,z) = Ʃm(1,2,3,7) and f2(x,y,z)= Ʃm(0,1,2,6) 8
using 3x4x2 PLA. Write the PLA table.
c Design a 2-bit comparator using logic gates 7
OR
2 a Apply decimal Quine-Mccluskey method to simplify the following Boolean 8
function. F(a,b,c,d) = Ʃm(0,1,2,6,7,9,10,12) + d(3,5)
b Design a combinational circuit using minimum number of NAND gates which takes 7
two, 2-bit binary numbers as its input and generates an output equal to 1, when the
sum of the two numbers is odd.
c Simplify the following expression using K-Map. 5
F(a,b,c,d) = ΠM(0,3,4,7,8,10,12,14)+d(2,6)
 UNIT 2
3 a Convert JK flip-flop to AB flip-flop . Functional table of AB flip-flop is described in 6
the table 3b.

Table 3 b

b Explain the NAND gates structure of positive edge triggered D flip-flop with truth 8
table and timing diagram.
c Derive the characteristic equation for SR and T flip-flops 6
UNIT 3
4 a A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is initialized 10
to a value 1000 for (Q0Q1Q2Q3). The D input is derived from Q0,Q2 and Q3 through
two XOR gates as shown in Figure 4a . Assume propagation delays of the gates are
zero.

Figure 4a.
i. Write the 4-bit values (Q0Q1Q2Q3) after each clock pulse till the pattern
1000 reappears on (Q0Q1Q2Q3).
ii. To what values should the shift register be initialized so that the pattern
1001 occurs after the first clock pulse.

b Design a counter using T flip-flops with the following binary sequence: 0,4,2,1,6 10
and repeat.
 UNIT 4
5 a Design a sequential circuit that adds two 5- bits of data using Moore circuit. Data is 12
sent to the circuit 1-bit per clock cycle.
b Using state table reduction technique, reduce the following state table. Analyze the 8
state table and find the output sequence for an input sequence of 01110010011
with starting state as 'a'.

Present Next state Output

state X=0 X=1 X=0 X=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
OR
6 a Analyze the synchronous sequential circuit shown in Figure 6a. Obtain its state table 10
and the state diagram.

Figure 6 a
b Design a synchronous circuit using positive edge triggered JK flip-flops with 10
minimal combinational gating to generate the following sequence.
0-1-2-0 if the input X=0 and
0-2-1-0 if the input X=1
provide an output which goes high to indicate non-zero states in the 0-1-2-0
sequence.
 UNIT 5
7 a Implement CMOS inverter, CMOS NAND and NOR gates. 10
b What are the different types of output configuration in TTL?. Explain Totem-Pole 10
NAND gate output with neat diagram
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