TUTORIAL

CCB1223 DIGITAL LOGIC

CHAPTER 5: COMBINATIONAL LOGIC ANALYSIS

1) Use AND gates, OR gates, and inverters to implement the following logic
expressions as stated:

X = A𝐂𝐂�+ 𝐁𝐁
�C

2) Draw the logic circuit for output X of the truth table in Table 1. Use a K-map and
simplify it.

Inputs Outputs
A B C X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

Table 1

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CHAPTER 6: FUNCTIONS OF COMBINATIONAL LOGIC

3) Figure 2 shows the pin and logic diagram of the 74HC147 decimal-to-BCD encoder
(HPRI means highest value input has priority). Determine the A3 A2 A1 A0 output
when LOWs are applied to these pins 11, 12, 13 and 1.

Figure 2

4) A 4-bit comparator in shown in Figure 3, plot each output waveform (A > B, A =

B, A < B) for the inputs shown by completing the waveforms in Figure 4. The
outputs are active-HIGH.

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 Figure 3

INPUTS

A<B

OUTPUTS A=B

A>B

Figure 4

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CHAPTER 7: LATCHES, FLIP-FLOP AND TIMERS

5) List THREE (3) types of latches.

6) Figure 5 shows a gated D latch. Determine the output waveform, Q if the inputs
shown in Figure 6 are applied to the latch, which is initially RESET.

Figure 5

Figure 6

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7) Determine the Q waveform relative to the clock if the signals shown in Figure 7
are applied to the inputs of the J-K flip-flop. Assume that Q is initially LOW.

Figure 7

CHAPTER 8: COUNTER

8) The waveforms in Figure 8 are applied to the counter CTEN, CLR, and CLK
inputs as indicated. Draw the counter output waveforms, Q0, Q1, Q2 and Q3 in
proper relation to these inputs. The CLR input is asynchronous.

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 Q0
Q1
Q2
Q3
Figure 8

9) Modify the design of the counter in Figure 9 to achieve a modulus of 30,000.

Ubahsuai rekabentuk pembilang dalam Rajah 9 untuk mendapatkan modulus 30,000.

Figure 9

CHAPTER 9: SHIFT REGISTER

10) What determines the storage capacity of a shift register.

11) Develop the logic diagram for the shift register in Figure 10, using J-K flip-flops
to replace the D flip-flops.

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 Figure 10

12) For the data input and clock in Figure 11, determine the states of each flip-flop in
the shift register of Figure 10 and show the Q waveforms. Assume that the register
contains all 1s initially.

Q0

Q1

Q2

Q3

Figure 11