PUSAT PENGAJIAN SAINS FIZIK

Universiti Sains Malaysia

2EL11-Digital Electronic – Adder and Flip-Flop Circuits

Part 1 – Adder circuit

Introduction
In digital electronic, operations such as add, subtract, multiply or divide which involve
binary numbers of 0 and 1 can be performed through the adder circuit. Adders are used in
the arithmetic logic unit (ALU) and also in other part of a processor such as counter. Basic
adder circuits are half adder circuit and full adder circuit, and the ALU circuit is basically
a combination of many full adders.

Half Adder Circuit

This circuit is capable of adding two-bit binary numbers at a time. For example, A and B
represent the two binary numbers to be calculated a sum of both. As a result, there are four
adder sequences as listed in Table 1.

Table 1 – Truth table of a half adder circuit

Input Output

A B Carry Sum

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Based on the truth table above, the sum or total is the output from the EXCLUSIVE-OR
get and carry is the output from the AND get. The actual process of adding two binary
numbers can be implemented by the half adder circuit as in Figure 1.

Figure 1

Revised & translated by Ong LH (2012) 1

Full Adder Circuit
In comparison, a full adder circuit is capable of adding three bits at a time. Full adder
circuit can be formed by joining two half adders and a OR gate as shown in Figure 2. This
can be illustrated that A, B and Cin are inputs to the full adder circuit in binary form.
As an example, if the three inputs A, B and Cin are of binary 1, then the addition process
can br implemented by the circuit is as follow:

A + B + Cin = 1 + 1 + 1 = 1 : 1 (carry : total)

Details as follow: 1 (A)
+ 1 (B)
1 : 0 (Carry : Sum) --first half adder
+ 1 (Cin)
1 : 1 (Carry : Sum) --second half adder

A full adder circuit can be designed using a combination of basic gates or even with
particular universal gates NAND or NOR only.

Figure 2

Table 2- Truth table of a Full Adder Circuit

Input Output
A B Cin Carry, Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Revised & translated by Ong LH (2012) 2

To add two 2-bit binary numbers A2A1 and B2B1, two full adders are needed as illustrated
in Figure 3. The outputs, J2 and J1 are the sum for the 2-bit binary numbers. By increasing
the number of full adders, the sum of any binary numbers can be determined.

Figure 3 – Adding A2A1 + B2B1

Objective
To understand the process of addition of binary numbers through the functions of half
adder and full adder circuits.

Apparatus:
Circuit evaluator IDL-800 Digital Lab
Integrated circuit (7400 and 7402)
Bread board
Connecting wire

Method:
1. Construct a half adder circuit by using only NAND gates, as shown in Figure 4. Then
verify and complete the truth table shown in Table 3.

Figure 4

Revised & translated by Ong LH (2012) 3

 Table 3 - Truth table of a half adder circuit
Input Output
A B Carry, Cout Voltage Sum Voltage
0 0
0 1
1 0
1 1

2. Design the half adder circuit by using only NOR gates, and confirm the truth table.

3. Design the full adder circuit by using any suitable logic gates, and verify its truth table.
Table 4 - Truth table of a Full Adder Circuit
Input Output
A B Cin Carry, Cout Voltage Sum Voltage
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Part 2 - Flip-Flop Circuit

Introduction
The flip-flop or latch circuit has two stable states. It is used in digital systems as a
temporary memory device or as part of the counter circuit. It is available in the form of
integrated circuits (IC's) produced by several manufacturers with codes such as 7473, 7474
and 7476. Basically the flip flop can be either simple (asynchronous) or clocked
(synchronous). The simple flip-flop without clock signal is called a latch.

The R-S latch is the R-S flip-flop without clock signal. R-S flip-flop with the clock signal
is also known as clocked-R-S flip-flop. In the absence of clock signal, the output of the
clocked-R-S flip-flop does not change despite the input R or S has varied. This output will
only change when the clock pulse arrives. The other types of flip-flops are D flip-flop,
toggle (T) flip-flop and J-K flip-flop. Each flip-flop has its strengths; J-K flip-flop may be
more suitable in the counter circuit and the D flip-flop in the register circuit.
Revised & translated by Ong LH (2012) 4
SET (S) and RESET (R) are the inputs of the R-S latch; and the changes in output depend
on the inputs in R and S. (see Figure 1). In a R-S latch, the two gates are connected by
cross-coupling output of the first gate to the input of the second gate, and the output of the
second gate returns to the input of the first. So when one of the gates is conducting, the
other will not be conducting. This means that the output is complementary and is denoted
by Q and Q . The reference set and reset logic is used to express the logic condition. Set is
Q = 1 and Q = 0. , while RESET is the opposite, which is Q = 0 and Q = 1.

Objective
To construct the R-S latch and R-S flip-flop using either NAND or NOR gates, and to
investigate the functions and operations of the R-S latch and R-S flip flops from the
circuits constructed.

Apparatus
Circuit evaluator IDL-800 Digital Lab
Integrated circuit (7400 and 7402)
Bread board
Connecting wire
Resistor 470 Ω

Methods
A. R-S latch
1. Construct the R-S latch circuit using NOR gates (7402), as shown in Figure 5.
2. Turn on the power supply. Connect Q and Q to the LED 1 to LED 2, respectively.
Logic 0 was put on inputs R and S. What happens to the LED 1 and LED 2? Record the
results in the R-S latch truth table.

Table 5- Truth table of a RS latch

Input Output Comment
R S Q Q

0 0 Q Q Hold state
0 1 1 0 Set
1 0 0 1 Reset
1 1 * * Racing

Revised & translated by Ong LH (2012) 5

 Figure 5

3. Apply logic 0 and 1 at inputs R & S respectively and observe the output to see whether
the results agree with Table 5. Then, draw the truth table of the latch from your
observation of this experiment.

B. R-S Flip-flop
1. Construct the RS latch using NAND gates (7400) as shown in Figure 6.

Figure 6

Table 6- Truth table of a clocked RS flip-flop (NAND gates)

Input Output before clock signal Output after clock signal
R S Q Q Q Q
0 0 1 0
0 1 1 0
1 0 1 0
1 1 1 0
0 0 0 1
0 1 0 1
1 0 0 1
1 1 0 1
2. Connect inputs S and R to the switches and Q and Q to the LEDs. Turn on power
supply and set the output Q =1 and Q =0, and set the inputs S =0 and R =0. Switch on the
clock and record the output, after the clock signal is on, into the truth table.
Revised & translated by Ong LH (2012) 6
3. By maintaining the circuit, return to the output Q =1 and Q =0 and repeat step 2 with
by setting the inputs S-R set to logic 0-1, 1-0 and 1-1.

4. Next, set the output Q =0 and Q =1, when the clock is off, and set the inputs S =0 and
R =0. Switch on the clock and record the output, after the clock signal is on, into the truth
table.

5. Return to the output Q =1 and Q =0 and repeat steps 4 for S-R: 0-1, 1-0 and 1-1.

6. Construct the flip-flop circuit using AND (7408) and NOR (7402) gates as shown in
Figure 7.

CLK

Figure 7

7. Repeat the procedure from step 2 to step 5 and build a truth table label as Table 7.
Table 7- Truth table of a clocked RS flip-flop (AND/NOR gates)
Input Output before clock signal Output after clock signal
R S Q Q Q Q
0 0 1 0
0 1 1 0
1 0 1 0
1 1 1 0
0 0 0 1
0 1 0 1
1 0 0 1
1 1 0 1

Revised & translated by Ong LH (2012) 7

ATTENTION
• Discuss whether the theoretical results agree with experimental outcomes. Please
provide a brief discussion on the problems faced during the experiment and suggest
ways to overcome them.
• What are the precautions that you have taken to prevent the equipment from
damage?
• Record the reference materials that you have used.

Appendix
Record the family of logic gates (IC family) used:______________________
With reference to the data sheet of TTL (Transistor-Transistor Logic), specify the values
of the proposed voltage range suitable and safe for the chip function. Fill in the table
below:

Symbols Definition Max. Min. Typical Unit

Vsupply Supply Voltage
VIH High level input voltage
VIL Low level input voltage
VOH High level output voltage
VOL Low level output voltage

Boolean algebra De Morgan's Theorem

A+B=B+A AB = BA = =
A =A A =A
A + (B + C) = (A + B) + C A(BC) = (AB)C
____ _ _ ____ _ _
A(B + C) = AB + AC A + BC = (A + B)( A + C) A+B = A.B A .B = A + B
A+0=A A.1 = A A + AB = A A(A + B) = A
A+1=1 A.0 = 0 _ _
A+A=A A.A = A A+AB = A + B A (A + B) = AB

− −
A+ A =1 A .A = 0

Revised & translated by Ong LH (2012) 8