EE220L DLD Lab Manual Fall 2022

Digital Logic Design Lab
Manual
EE-220L
Fall 2022
University of Management & Technology

School of Engineering
Department of Electrical Engineering
Name : ________________________
Student ID : ____________________
Section : _______________________
EE-220L Digital Logic Design
University of Management and Technology

School of Engineering
Department of Electrical Engineering
Course Outline
Course Code: EE 220L Course Title: Digital Logic Design Lab
Program BS EE
Credit Hours 1
Duration One semester
Prerequisites Nil
Resource Persons M. Asad Ali (A1,A2)
Counseling Timing See Office Window
Email asad-ali@umt.edu.pk
Chairman/Director signature………………………………….
Dean’s signature……………………………
Date………………………………………….
1
Learning Objectives:
The objective of this lab is to introduce students with basic digital logic design concepts and
to implement them as well. Labs are designed in such a way that at the end students will be
able to know the following terms
• Verification of basic binary operators and basic theorems using gates.
• Understanding of gates.
• Design of combinational circuits.
• Implementation of Adder and Subtractor circuits.
• Implementation of Encoder, Decoder, Multiplexer and Demultiplexer.
• Verification of Latch’s and Flip Flops.
• Design of Sequential Circuits
• Implementation of series and parallel registers
• Implementation of asynchronous and synchronous counters
In accordance with HEC curriculum outcomes a, b, d, e, g, h & i, students at the end of the
course should be able to
• To practically know and perform the digital logic design concepts

• To have thorough understanding of digital logic design principles
• To have basic problem solving and troubleshooting techniques
Learning Methodology:
Lecture, interactive, participative
Grade Evaluation Criteria:

Following is the criteria for the distribution of marks to evaluate final grade in the semester .
Marks Evaluation Marks
Lab Manuals & Performance: 50
Term Project 10
Final Viva + Performance: 20 + 20
Total: 100
2
Recommended Text Books:
Digital Design, Edition by Morris Mano and Michael D. Ciletti
Reference Books:
Digital Design, Principles & Practices, Edition by John F. Wakerly
Course Learning Outcomes (CLOs):
CLO 1: Construct / build and troubleshoot different digital circuits using basic gates.
CLO 2: Analyze the different small-scale combinational and sequential digital circuits.
CLO 3: Demonstrate responsible attitude in lab execution.
CLO 4: Synthesize experimental results through technical report.
CLO 5: Demonstrate teamwork while working towards project deliverables.
Relation to EE Program Learning Outcomes (PLOs):
Related Levels of
CLOs Teaching Methods CLO Attainment checked in
PLOs Learning
CLO 1 PLO 3 Psy-4 Instructions Lab Work Lab Sessions, Exam
CLO 2 PLO 4 Cog-3 Instructions, Lab Work Lab Sessions, Exam
CLO 3 PLO 8 Aff-3 Instructions, Lab Work Lab Sessions
CLO 4 PLO 10 Aff-4 Instructions, Lab Work Lab Reports
CLO 5 PLO 9 Aff-3 Group Project Project Deliverables
3
Calendar of Course contents to be covered during semester
Course Code: EE-220L Course title: Digital Logic Design Lab

Relevance to
Week Lab Experiments
Theory Topics CLOs
Verification of basic binary operators and basic TB: Article 2.2
1 1,2,3,4
theorems using gates – 2.8
2 Universality of NAND and NOR gates TB: Article 3.7 1,2,3,4

Implementation of Full Adder and 4-bit Parallel
3 TB: Article 4.5 1,2,3,4
Adder using IC 74283
Implementation of Full Subtractor and 4-bit Parallel
4 TB: Article 4.5 1,2,3,4
Subtractor using IC 74283
Implementation of combinational circuits
5 TB: Article 4.2 1,2,3,4
(Open-Ended Lab)
TB: Article
6 Implementation of code converters using gates 1,2,3,4
4.4, 4.6
Implementation of Encoder and Decoder using IC TB: Article 4.9
7 1,2,3,4
74138 & 74148 – 4.10
8 Mid-Term Examinations
Implementation of Multiplexer and Demultiplexer

9 TB: Article 1,2,3,4
IC74151&74138
4.11
Verification of Latch and Flip Flop operation using TB: Article 5.3
10 1,2,3,4
gates and flip flop’s IC -5.4
11 Implementation of Sequential Circuits TB: Article 5.8 1,2,3,4

TB: Article 6.1
12 Implementation of series and parallel registers 1,2,3,4
– 6.2
Implementation of asynchronous and synchronous TB: Article 6.3
13 1,2,3,4
counters – 6.4
Implementation of RAM and ROM using gates and
14 TB: Article 7.2 1,2,3,4
Static RAM IC
Material will
15 Implementation of LAMP HAND BALL game 1,2,3,4
be provided
4
16 Term Project Evaluation All concepts 1,2,3,4,5
Complex Engineering Problem/Activity:
Complex Engineering Problem Included: No

Details
Complex Engineering Activity Included: No

Details
5
EL-220 Digital Logic Design Lab Evaluation Rubric
Lab # Lab Title : Section :
Analyze the
Implementation of Logic circuit Ability to Debug Illustrate experimental
outcome Punctuality Behavior in Lab
Areas Assessed Lab Work Organization Logic circuits results through report CLO wise Total
of the circuits
(CLO 1) (CLO 1) (CLO 1) (CLO 2) (CLO 3) (CLO 3) (CLO 4)
Logic circuit was
Logic circuit was Wasn’t able No analysis on the No care of equipment and Wasn’t able to
not
Poor (0 to 40%) not to debug the results obtained work-station with components summarize the
properly
properly functional Logic circuit in the lab Not on not returned after use experiment
organized
Time Total
Reasonable Appropriate care of equipment
Logic circuit was Debugged the Was able to
Logic circuit was interpretation and work-station with
Satisfactory (40 to 75%) somewhat Logic circuit with summarize some CLO 1 CLO 2 CLO 3 CLO 4
somewhat neat of results components
functional assistance of the experiment(s)
obtained returned after use
Debugged the Thorough
Thorough understanding
Logic circuit was Logic circuit understanding Proper care of equipment and
Logic circuit was of
Very Good (75 to 100%) properly successfully of the results On Time work-station with components
fully functional every aspect of
organized without obtained in the returned after use
experiments conducted
assistance lab
Maximum Marks ►
Sr #
3 1 1 2 0.5 0.5 2 5 2 1 2 10
Student ID▼ Student Name▼
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 0
4 0 0 0 0 0
5 0 0 0 0 0
6 0 0 0 0 0
7 0 0 0 0 0
8 0 0 0 0 0
9 0 0 0 0 0
10 0 0 0 0 0
11 0 0 0 0 0
12 0 0 0 0 0
13 0 0 0 0 0
14 0 0 0 0 0
15 0 0 0 0 0
16 0 0 0 0 0
17 0 0 0 0 0
18 0 0 0 0 0
19 0 0 0 0 0
20 0 0 0 0 0
EL-220 Digital Logic Design Lab 1
VERIFICATION OF BASIC BINARY OPERATORS AND BASIC THEOREMS

USING GATES
Relevant Theory Topics: Introduction to digital logic, Number system and codes,
Binary storage and binary logic, Boolean algebra (Ref er to Chapter 1 & 2 of Digital
design, Edition by Morris Mano)
APPARATUS / COMPONENTS
1. Digital Logic Trainer
2. IC 7408, IC 7432, IC 7404, IC 7400, IC 7402 and IC 7486
(PART A)
OBJECTIVE:
Familiarization with the AND, OR, NOT, NAND, NOR and XOR gates.
TASK 1: LOGICAL “AND” OPERATION

The AND operation produces an output of 1 (or high) when all of the inputs are 1 (or
high). It produces an output of 0 (or low) when any or all of the inputs are 0 (or
low). Symbol f or “Two Input AND Gate” and “Truth Table” f or AND operation is as
given below:
Symbol of AND gate Truth Table for AND operation
Inputs Outputs
Desired
A B Observed
x= A . B
0 0 0
0 1 0
1 0 0
1 1 1
PROCEDURE
1. Insert the IC 7408 on the trainer’s breadboard.

2. Use any two Logic Switches (S2 to S9) of the trainer f or Input and any o ne of
the LEDs (L0 to L15) of the trainer f or Output indication.
3. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
Page 0 of 104
EE-220L Digital Logic Design Lab 1
4. By setting various combinations of the two switches verif y that the output of
the AND gate is in accordance with the Truth Table shown above. Record your
observation.
TASK 2
▪ Repeat Task 1 f or IC 7432, IC 7404, IC 7400, IC 7402 and IC 7486. Draw
truth table and show your results to lab instructor [For IC conf iguration see
datasheet].
(PART B)
OBJECTIVE
To verif y Theorems of Boolean Algebra through Logic Circuits.
TASK 3: VERIFICATION OF ABSORPTION THEOREM
 Verif y Absorption Theorem A + (A . B) = A

 Show your results to the lab instructor.
Inputs Output
A B Observed
0 0
0 1
1 0
1 1
 Draw Circuit Diagram.
Page | 1
 Verif y Absorption Theorem A. (A + B) = A
Inputs Output
A B Observed
0 0
0 1
1 0
1 1
 Draw Circuit Diagram.
Page | 2
PIN Configurations
Below are the pin configurations for different logic gates. They will be
helpful to your during your lab work.
Page | 3
LAB ASSIGNMENT
1. What kind of logic operation does this chip perform?

Ans: ____________________
2. How many logic gates does this chip contain?
Ans: ____________________
3. Select one more two-input 74xx family IC. Fill in the following table
and write down the IC number and the function of that IC.
IC No: _____________
Function: _____________
Inputs Output
X Y F
0 0
0 1
1 0
1 1
4. Verify DeMorgan’s Law. Show Truth Table and Cir cuit Diagram.
Page | 4
Observations/Comments/Explanation of Results
(Please write in your own words the objectives and yours learning during the
experiment. Also explain the results and comment on it.)
Page | 5
EE-220L Digital Logic Design LAB 2
UNIVERSALITY OF NAND AND NOR GATES
2. IC 7400, 7402
Relevant Theory Topics: NAND, NOR and XOR Implementation, Two level
implementation (Refer to Chapter 03 of Digital design, Edition by Morris Mano)
OBJECTIVE
To learn the implementation of any logic expression by using only NAND or NOR
gates.
THEORY
Digital circuits are more f requently constructed with NAND or NOR gates than with
AND and OR gates. NAND and NOR gates are easier to f abricate with electronic
components and are the basic gates used in all IC digital logic f amilies. Because of
the prominence of NAND and NOR gates in the design of digital circuits, rules and
procedures have been developed f or conversion f rom Boolean f unction given in terms
of AND, OR, and NOT into equivalent NAND and NOR logic diagram.
TASK 1: NAND GATE IMPLEMENTATION OF BOOLEAN FUNCTIONS
If we can show that the logical operations AND, OR, and NOT can be implemented
with NAND gates, then it can be saf ely assumed that any Boolean f unction can be
implemented with NAND gates. Figure-1 below shows such implementation:
Figure 2a: AND gate operation
Figure 2b: OR gate operation
Page | 6
Figure 2c: NOT gate operation

PROCEDURE
1. Insert the IC on the trainer’s breadboard.

2. Use any one or more of the NAND gates of the IC f or this experiment.
3. Any one or more Logic Switches of the trainer (S2 to S9) can be used f or
input to the NAND gate.
4. For output indication, connect the output pin of the circuit to any one of the
LEDs of the trainer (L0 to L15).
5. Connect the circuit as per Fig. 2(a) above.
6. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
7. By setting the switches to 1 and 0, verif y that the output of the circuit
conf orms to that of an AND gate. Record your observation in the table below:
Inputs Output
Desired
A B Observed
x=A.B
0 0 0
0 1 0
1 0 0
1 1 1
 Verif y OR gate operation using NAND gates (See Fig. 2b).

Inputs Output
Desired
A B Observed
x=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Page | 7
 Verif y NOT gate operation using NAND gates (See Fig. 2c).
Inputs Output
Desired
A Observed
X=A'
0 1
1 0
TASK 2: ALTERNATE LOGIC GATE REPRESENTATION
It is becoming increasingly more common to use alternate logic symbols in logical

circuit diagrams, in addition to the standard symbols. Proper use of alterna te gate
symbols in the circuit diagram can make the circuit operation much clearer.
Alternate symbols of the basic gates are given below. Find out which gate each of
these represents.
Inputs Output
A B Observed
0 0
0 1
1 0
1 1
Above mentioned alternate logic gate is equivalent to _________ gate.
Inputs Output
A B Observed
0 0
0 1
1 0
1 1
Page | 8
Inputs Output
A Observed
0
1
LAB ASSIGNMENT
1. Implement AND, OR and NOT operation using NOR gate. Show truth
table and logic diagram.
2. Find the equivalence of the following alternate logic gate. Also show
truth table.
Page | 9
Page | 10
IMPLEMENTATION OF FULL ADDER AND 4-BIT PARALLEL ADDER USING IC
7483
(1) Digital Logic Trainer

(2) IC 7408, 7404, 7483& IC 7486 (pin conf iguration shown in appendix)
Relevant Theory Topics: Adder/ Subtractor (Refer to Chapter 04 Digital design,

Edition by Morris Mano)
OBJECTIVE
1. To learn Half and Full Adder Operations.

2. To learn 4- Bit Binary Parallel Adder Operations.
THEORY
Digital computers perf orm a variety of inf ormation-processing tasks. Among
the basic f unctions encountered are various arithmetic operations. The most basic
arithmetic operations are, no doubt, the addition and subtraction of binary digits
(bit).
a. Half Adder :
The possible operations, when we want to add only two bits,
would be the f ollowings:
0+ 0=0
0+ 1= 1
1+ 0= 1
1+ 1= 0 & Carry 1
Above mentioned operation could be perf ormed by a Half Adder circuit.
b. Full Adder :
We know that in practice, all addition operations must take into account the
Carry bit (or digit) f rom the previous operation. Adders in digital computers
also take into account the Carry bit f rom last operation and add it with the
Augend and Addend bits of the present operation to complete the addition
operation. The possible operations are:
0 + 0 + 0 (carry) = 0
0 + 0 + 1 (carry) = 1
0 + 1 + 0 (carry) = 1
0 + 1 + 1 (carry) = 0 & carry 1 (to be added to next higher digit)
Page | 11
The adder that perf orms the addition of three bits (two signif icant bits and a
previous carry) is called a Full Adder.
TASK 1: HALF ADDER.

We arbitrarily assign symbols A and B to the two inputs and S (f or sum) and Cout
(f or Carry) to the two outputs. Truth table f or Half Adder as shown below: -
Output
Input Observed
Desired
A B S Cout S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 1: Truth Table f or Half Adder operation
The simplif ied Boolean f unction f or the two outputs can be written f rom this truth
table as:-
S = A'.B +A.B' or A B
Cout = A.B
The circuit diagram f or the Half Adder to implement above mentioned Boolean
f unction could be quite a f ew. We will however verif y only one.
Figure 1: Half Adder using AND and XOR gates.
PROCEDURE
1. Wire the circuit as per f igure 1 above.

2. Use any two Logic Switches of the trainer (S2 to S9) f or the input and any
two of the LEDs of the trainer (L0 to L15) as output indication.
Page | 12
3. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the ICs.
the circuit is in accordance with the Truth Table shown above. Record your
observation.
TASK 2: FULL ADDER.

As mentioned in the beginning, a f ull-adder is a combinational circuit that
f orms the arithmetic sum of three input bits (two signif icant bits and a
previous carry bit) and two output bits. We arbitrarily assign symbols A
and B to the two signif icant bit inputs and Cin f or the Carry f rom the
previous lower signif icant position, and S (f or sum) and Cout (f or Carry) to
the two outputs. Truth table f or the Full Adder is shown below:
Output Output
Input
Desired Observed
A B Cin S Cout S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simplif ied Boolean f unction f or the two outputs can be written f rom this truth table
as:-
S =( A B) Cin
Cout = (A B) Cin + A.B
Page | 13
The circuit diagram f or the Full Adder is as under:
Figure 2: Full Adder comprising of two Half Adders and an OR gate.
PROCEDURE

2. Use any three Logic Switches of the trainer (S2 to S9) f or the input and any
two of the LEDs of the trainer (L0 to L15) as output indication.
3. Connect +5V to pin 14 (V cc) and Ground to pin 7 (GND) of the ICs.
observation.
Page | 14
TASK 3: 4 BIT BINARY PARALLEL ADDER
Adders that are available in integrated circuit f orm, are parallel binary adders. A 4-
Bit parallel adder consists of f our f ull adders connected in parallel. The carry output
of each adder is internally connected to the carry input of the next higher order
adder. Fig 3 shows the internal f unctional structure of 74283 IC in which 4 f ull
adders are shown as separate entity. Figure 4 is connection diagram f or f ull adder
f unction.
Figure 3: IC 74283 Internal Functional Structure
Figure 4: Connection Diagram f or 4-Bit Parallel Adder
Page | 15
PROCEDURE

2. Use f irst f our Logic Switches of the trainer f or the inputs A0 to A3, and next
f our switches f or inputs B0 to B3.
3. Connect Cin (pin 7) to GND (we are assuming initial carry to be zero).
4. Use f irst f our LEDs of the trainer to indicate Sum outputs S0 to S3, and
another LED to indicate status of the most signif icant carry bit Cout .
5. Connect +5V to pin 16 (Vcc) and Ground to pin 8 (GND) of the ICs.
6. By setting various combinations of the two sets of input switches verif y that
the output of the circuit is in accordance with the Table shown below (only
f ew of the possible additions have been shown here). Record your
observation.
Inputs Desired Output Observed Output

Decimal Decimal
Binary Augend Binary Addend Value Binary Output value Binary Output
f or Ref f or Ref
A3 A2 A1 A0 B3 B2 B1 B0 A B Co S3 S2 S1 S0 Sum Co S3 S2 S1 S0
0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 2
0 0 1 1 0 0 0 1 3 1 0 0 1 0 0 4
0 1 0 0 0 0 1 0 4 2 0 0 1 1 0 6
0 1 0 0 0 1 0 0 4 4 0 1 0 0 0 8
0 1 0 1 0 1 0 0 5 4 0 1 0 0 1 9
0 1 0 1 0 1 0 1 5 5 0 1 0 1 0 10
1 0 0 0 0 1 0 0 8 4 0 1 1 0 0 12
1 0 0 1 0 1 1 0 9 6 0 1 1 1 1 15
1 0 0 1 1 0 0 0 9 8 1 0 0 0 1 17
1 0 0 1 1 0 0 1 9 9 1 0 0 1 0 18
Page | 16
Page | 17
IMPLEMENTATION OF FULL SUBTRACTOR AND 4-BIT PARALLEL
SUBTRACTOR USING IC 74283
Relevant Theory Topics: Design of combinational logic Adder/ Subtractor (Refer to

Article 4.4, 4.5 Digital design, Edition by Morris Mano)
In binary subtraction, when larger digit is to be subtracted f rom a smaller digit, it
becomes necessary to BORROW a value f rom the next higher position. Thus the
binary subtraction results in the f ollowing basic operations
0-0= 0
0 - 1 = 1, with a 1 borrowed f rom next higher digit position (which became 11 binary
on reaching current position).
1-0= 1
1-1= 0
The arithmetic element that perf orms this subtraction operation is called a Half
Subtracter.
a. Full Subtractor:
When we have borrowed a value f rom a higher position, then it must be
accounted f or when subtraction is perf ormed at that higher position. The way
it is done can be explained with the f ollowing example:-
Posn 4 Posn 3 Posn 2 Posn 1 Posn 0

Minued 26 = 1 1 0 1 0
Subtrahend - 12 = 0 1 1 0 0
------- ---------------------------------------------
14 = 0 1 1 1 0
At position 2 we borrowed a “1” f rom position 3 to carry out subtraction. When we move to position 3
f or subtraction, the position 2 should have returned the borrowed “1”, which will be added
to the Subtrahend at position 3. (Note: Minuend at Posn3 will remain 1)
We need to have two arrangement to carry out above mentioned action: first, in-
addition to the subtraction result (call it Do), the Position2 should give out another
output as high (or 1) (call it Bo- borrow out) which would indicate its obligation to return
the borrowed “1” to position 3; second, position three should have some input
arrangement (call it Bin – borrow in), which would take the “1” returned by position 2 and
add it to the Subtrahend of position 3.
Page | 18
The possible combinations f or f ull subtraction would be;

0 - 0 with a 0 as Bin = 0
0 - 0 with a 1 as Bin = 1, only if a 1 is borrowed f rom next higher digit position
0 - 1 with a 1 as Bin = 0, only if a 1 is borrowed f rom next higher digit position.
The arithmetic element that perf orms this subtraction operation is called Full
Subtractor.
TASK1.
Implement Half subtractor.
Truth Table:
Page | 19
Logic Diagram:
TASK2.
Implement Full Subtractor
Truth Table:
Page | 20
Logic Diagram:
Page | 21
LAB ASSIGNMENT
Task 1:
Implement 4-bit parallel SUBTRACTOR operation using combination of half
subtractor & full subtractors only.
Page | 22
LAB ASSIGNMENT
Task 2:
Implement 4-bit parallel SUBTRACTOR operation using Full Adders only.
Page | 23
LAB ASSIGNMENT
Task 3:
Implement 4-bit parallel Adder & Subtractor operation using IC 74283 only.
Figure : Connection Diagram f or IC 74283
Page | 24
Page | 25
IMPLEMENTATION OF COMBINATIONAL CIRCUITS (Open Ended Lab)
Introduction:
A combinational circuit is a circuit made up by combining logic gates such that the
required logic at thorough put(s) depends only on the input logic present condition,
both completely specif ied by either a truth table or by a Boolean expression.
Relevant Theory Topics: The map method, Combinational logic Analysis, Design of
combinational logic (Refer to Article 3.1, 3.2, 3.3, 4.1-4.5 of Digital design, Edition by
Morris Mano)
Characteristics
1. An output(s) remains constant, as long input conditions do not require change
in output(s).
2. An output depends solely on the current input condition and not on any
past………………………………………………………………………………………………………………………
…………………….. input condition or past output condition.
Task 1:
Truth Table:
Page | 26
Simplification using K-map:
Boolean Function:
Page | 27
Logic Diagram:
Page | 28
LAB ASSIGNMENT
Page | 29
Page | 30
IMPLEMENTATION OF CODE CONVERTERS USING GATES
2. IC 7447, IC 7486, AND, OR and NOT gates
3. 7-Segment Display
4. Resistors 180 Ohms
Relevant Theory Topic: Binary Codes, K-Map implementation (Refer to Article 1.7,
3.2, 3.3, of Digital design, Edition by Morris Mano)
OBJECTIVE
To learn about BCD to Seven Segment Display Code, Gray Code and Excess -3 Code
Conversion.
THEORY
The availability of large variety of codes f or the same discrete elements of
inf ormation results in the use of dif f erent codes by dif f erent digital systems.
Sometimes it becomes necessary to use output one system as input to another
system. A conversion circuit must be inserted between the two systems, if each uses
dif f erent code f or the same inf ormation. When a decimal number is decoded such
that each digit of the number is represented by a 4-bit binary number, it is called an
8421 Binary Coded Decimal Code or more simply a BCD code. Here, ten out of
sixteen possible combinations of the code are selected to represent decimal 0
through 9. Most commonly used BCD codes are given below:
DECIMAL BCD GRAY CODE EXCESS-3 CODE

0 000 0 000 0 001 1
1 000 1 000 1 010 0
2 001 0 001 1 010 1
3 001 1 001 0 011 0
4 010 0 011 0 011 1
5 010 1 011 1 100 0
6 011 0 010 1 100 1
7 011 1 010 0 101 0
8 100 0 110 0 101 1
9 100 1 1 1 01 110 0
Page | 31
The important characteristics of the Gray code is that only one digit changes as we
count f rom top to bottom; that is why it is termed as minimum change code. The
Gray code is used f or input and output devices. Primary use is in numeric input
encoding applications, where we expect nonrandom input value change (i.e. value n
changes either to n-1 or to n+1). Another decimal code that has been used in some
old computers is Excess-3 code. Its code assignment is obtained f rom the
corresponding value of BCD af ter the addition of 3. The code is used in many
arithmetic circuits because it is self -complementing (i.e. the 9’s complement value of
the decimal number can be obtained by complementing each bit of the code).
TASK 1: BCD TO SEVEN SEGMENT DISPLAY CODE CONVERSION
Most Digital equipment has some means f or displaying inf ormation in a f orm that can
be understood readily by the user or operator. One of the simplest and most popular
methods f or displaying numerical digits uses a 7-segment conf iguration. To f orm
decimal characters 0 through 9 and sometimes hex characters A through F. A BCD
to 7-Segment Driver (IC 7447) is used to take f our bit BCD input and provide the
outputs that will pass current through the appropriate segment of the display to
generate desired output/ number. Truth Table f or Active High and Active Low cases
are shown below:
Output-Seven Segment Decoder
INPUT –BCD
Decimal
(Active High)
Display
So S1 S2 S3 a b C d e f g
Output
0 0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 1 0 1 1 0 0 0 0 1
0 0 1 0 2 1 1 0 1 1 0 1 2
0 0 1 1 3 1 1 1 1 0 0 1 3
0 1 0 0 4 0 1 1 0 0 1 1 4
0 1 0 1 5 1 0 1 1 0 1 1 5
0 1 1 0 6 0 0 1 1 1 1 1 6
0 1 1 1 7 1 1 1 0 0 0 0 7
1 0 0 0 8 1 1 1 1 1 1 1 8
1 0 0 1 9 1 1 1 0 0 1 1 9
Page | 32
INPUT –BCD Output- Seven Segment Decoder (Active
Decimal
Low -IC 7447) Display
Output
S0 S1 S2 S3 a b c D e f g
0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 1 0 0 1 1 1 1 1
0 0 1 0 2 0 0 1 0 0 1 0 2
0 0 1 1 3 0 0 0 0 1 1 0 3
0 1 0 0 4 1 0 0 1 1 0 0 4
0 1 0 1 5 0 1 0 0 1 0 0 5
0 1 1 0 6 1 1 0 0 0 0 0 6
0 1 1 1 7 0 0 0 1 1 1 1 7
1 0 0 0 8 0 0 0 0 0 0 0 8
1 0 0 1 9 0 0 0 1 1 0 0 9
Figure 1: BCD to Seven Segment Converter Circuit.
The segments of Seven Segment display are made of LEDs. Depending on the
arrangements of the LEDs, the display could be Common Anode or Common Cathode
type. We are using common anode type of display, which would require that either
pin 3 or pin 8 is connected to Vcc and the input is active low.
Page | 33
PROCEDURE
1. Wire the circuit as per f igure 1 above. Connect pin 3 or pin 8 to Vcc.
2. By setting various combinations of the switches verif y the result.
TASK 2: BCD TO GRAY CODE CONVERSION

The bit combination f or the BCD and Gray code are listed in the table below. Since
each code uses f our bits to represent a decimal digit, there must be f our input
variables and f our output variables.
Input BCD Output Gray Code Observed Output
A B C D W x y Z W x y z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
With the help of K- Map, the simplif ied output can be obtained as:
w =A x=A’B+AB’=A B
Page | 34
y = BC’+B’C=B C z = CD’+C’D=C D
Figure 2: Logic Diagram f or BCD to Gray code converter.
PROCEDURE
1. Wire the circuit as per Fig. 2 above.

2. Use any f our Logic Switches of the trainer (S2 to S9) f or the input and any
f our of the LEDs of the trainer (L0 to L15) as output indication.
3. Connect +5V to pin 14 (V cc) and Ground to pin 7 (GND) of the ICs.
observation.
Page | 35
TASK 3: BCD TO EXCESS-3 CODE CONVERSION.
The bit combination f or the BCD and excess-3 codes is listed in the table below.
Since each code uses f our bits to represent a decimal digit, there must be f our input
and f our output variables.
Output Excess-3
Input BCD Observed Output
Code
A B C D w x y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
With the help of K- Map, the simplif ied output can be obtained as:
(1)w = A + BC + BD = A + B(C+D)(2) x = B'C + B'D + BC'D'

=B'(C+D)+BC'D'
=B'(C+D) +B(C+D)'
Page | 36
(3) y = CD + C'D' = CD + (C+D)' (4) z = D'
PROCEDURE
1. Wire the circuit as per above Fig. 3 and verif y the results.
Figure 3: Logic Diagram f or BCD to excess-3 code converter.
Page | 37
LAB ASSIGNMENT
1. Design BCD to 2421 convertor.
Page | 38
Page | 39
2. Design a circuit which calculates 9’s complement of a BCD number.
Page | 40
Page | 41
Page | 42
IMPLEMENTATION OF ENCODER AND DECODER USING IC 74138 & 74148
2. IC 74138 IC 74148
Relevant Theory Topics: Combinational logic Decoders, Encoders (Ref er Article
4.10, 4.11of Digital design, Edition by Morris Mano)
OBJECTIVE
To learn about Encoder and Decoder.
THEORY
▪ An encoder circuit has more input lines and
f ewer output lines.
▪ A decimal to BCD encoder (10 line to 4 line) will
convert (at any one time) one active input out
of ten to a BCD code output.
▪ An octal-to-binary encoder (8 line to 3 line) will
convert (at any one time) one-of -eight inputs
to a binary code output
▪ A decoder circuit f ew input lines and more
output lines.
▪ A binary-to-octal decoder converts 3 binary bits
into 8 outputs (only one which will be active at
one time)
▪ A BCD decoder converts a 4-bit BCD code on
into 10 output outputs (only one which will be
active at one time).
▪ A hexadecimal decoder converts a 4-bit binary
code on the input to a 1-of -16 output.
▪ Decoders are of ten used in microprocessor
systems to decode the address inf ormation
f rom the microprocessor in order to select the
correct memory chip.
Page | 43
DECODERS:
IC 74138 has been used here as a decoder. It has 3-Select Inputs and 8- Data
Outputs. Functional block diagram of IC 74138 is attached. Note that the IC 74138
has Enable Inputs which we will not use during decoder operation, theref ore we will
keep G1 as high and G2A and G2B as low so that the output of Enable gate remains
always high and does not interf ere with our desired result. Also note that the
output of the IC is active low. Connection diagram and Truth table of the IC
74138 when used as decoder is shown below:
Note: Output of the IC 74138 is active low, so the output line having a Zero
in the Truth Table will be selected
SELECT INPUT DATA OUTPUT

C B A O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
Wire the circuit as per f igure 1 above and verif y the results.
Page | 44
TASK 1: Implement a Full Adder using decoder (3 × 8) IC 74138 along
with NOT and OR gate ICs.
Page | 45
TASK 2: Implement a Full Adder using decoder (3 × 8) IC 74138 along
with NAND gate ICs. Hint : You can use Dual 4-input NAND IC 7420.
Page | 46
TASK 3: Implement a Full Subtractor using decoder (3 × 8) IC 74138
along with NOT and OR gate ICs.
Page | 47
TASK 4: Implement a Full Subtractor using decoder (3 × 8) IC 74138
along with NAND gate ICs. Hint : You can use Dual 4-input NAND IC
7420.
Page | 48
ENCODER
IC 74148 is a 8- Line-to- 3-line (octal to binary) Priority Encoder. It has 8 Inputs (0-
7), an Enable Input EI, an Enable Output EO, 3 Output (A0-A2), and a Gs Output.
Details as under:
▪ A0-A2 outputs ref lect a code that is equal to the highest valued active input.
▪ Gs output goes low any time any of the input goes low (this low signal is
used f or interrupt request to CPU, when connected f or the purpose).
▪ EI and EO are used f or cascading more than one 74148 together.
Functional block diagram of IC 74148 is attached. Connection diagram and Truth
table of is shown below:
INPUT OUTPUT
EI 0 1 2 3 4 5 6 7 A2 A1 A0 Gs Eo
0 X X x x x X X 0 0 1
0 X X x x x X 0 1 0 1
0 X X x x x 0 1 1 0 1
0 X X x x 0 1 1 1 0 1
0 X X x 0 1 1 1 1 0 1
0 X X 0 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 0 1
Wire the circuit as per f igure above and f ill in the blanks in the truth table.
Page | 49
TASK 5: Implement a (4 × 2) priority Encoder with input I3 at highest

priority.
Page | 50
Page | 51
IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER USING
IC74151& IC74138
2. IC 74151 & 74138
Relevant Theory Topics: Combinational logic Decoders, Encoders Multiplexer, De-

Multiplexers (Refer Chapter 4.9-4.11 Digital design, Edition by Morris Mano)
OBJECTIVE:
To learn about Multiplexer and Demultiplexer.
THEORY:
A. MULTIPLEXER:
1. The multiplexer circuit is used to place two or more digital signals (f rom two or
more sources) onto a single line, by placing them there at dif f erent time intervals
(technically it is known as time-division- multiplexing).
2. The multiplexer (also known as data selector) will select data f rom several
transmission lines to be gated to the single output transmission line.
3. The multiplexer will have a number of control inputs that are used to select the
appropriate data channel f or input.
4. The number of data inputs is equal to 2n where n is the number of control
selecting leads.
5. A multiplexer can be used to convert parallel data to serial data.
Page | 52
B. DEMULTIPLEXER:
1. A demultiplexer (data distributor) will receive inf ormation f rom a single
line and selectively transmits it to several output lines/channels (one at a
time).
2. Demultiplexer has several control select lines which are used to determine
(or select) the output transmission path.
3. The number of data output lines is 2n, where N is the number of control
select leads.
4. Demultiplexers are used to convert serial data to parallel data.
TASK 1: MULTIPLEXER.
IC 74151 is a 8-to-1-Line Multiplexer. It has f ollowing f eatures:-
1. 8 Data Inputs (DO-D7).
2. Three Select Inputs (A, B, C).
3. An Enable (or Strobe) G
4. A one bit output Y (and its complement W)
Page | 53
PROCEDURE
1. Wire the circuit as per f igure above.

2. Connect “Clock Input” (very low f requency) to Input pins of the IC (D0 – D1)
and see if the Output LED is pulsating. Conf irm your f inding on the truth
table.
Functional block diagram of IC 74151 is attached.

Connection diagram and Truth table is shown below:
Select Strobe Output Output

C B A G (or S) Y Observed
Output Y is linked with input present at
0 0 0 0
D0
0 0 1 0
D1
0 1 0 0
D2
0 1 1 0
D3
1 0 0 0
D4
1 0 1 0
D5
1 1 0 0
D6
1 1 1 0
D7
Page | 54
TASK 2: Implement a Full Adder using MUX (8 × 1) IC 74151.
Hint : You need two separate ICs to implement Sum and Carry Out.
Page | 55
TASK 3: Implement a Full Subtractor using MUX (8 × 1) IC 74151.
Hint : You need two separate ICs to implement Dif f erence and Borrow.
Page | 56
TASK 4: DEMULTIPLEXER
A 1-Line-to-8-Line demultiplexer distributes one input to 8 output lines. IC
74138 which was used as a decoder in the last experiment will be used here
as Demultiplexer. The only dif f erence between the previous circuit and
present circuit will be addition of an INPUT (through Enable AND gate) to the
4th pin of all the 8 NAND gates. The A, B and C inputs will serve as SELECT
input (to select a particular output line).
Note that the Enable Inputs of IC 74138 was not used during decoder operation. We
will now use G2B pin of the IC f or Data/Signal Input. We theref ore need
to keep pins G1 as high and G2A as low, so that the Input Data/Signal
remains present at output of Enable gate and consequently on the 4th input
pin of all the 8 NAND gates.
Connection diagram and Truth table of the IC 74138 when used as

demultiplexer is shown below. Clock signal (very low f requency) has been
used as Input (so that blinking of the LEDs can be observed):
Note: Output of the IC 74138 is active low , so the output line having a
Zero in the Truth Table will be selected
Page | 57
Input Output
C B A O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
Page | 58
TASK 5: DATA COMMUNICATION USING MULTIPLEXER & DEMULTIPLEXER.
Multiplexer IC 74151 and Demultiplexer IC 74138 has been utilized to demonstrate
single-line data communication. The 3-bit select code will determine which data input
will be steered to the Y output of the Demultiplexer.
Observed
Applied When Clock Signal is
Signal Out
Select Signal at Data Applied At All of D
at Output
Input Pin Pins of MUX
Pin
Observed Output at
C B A D Y
Pin of DEMUX
0 0 0 D0 Y0
0 0 1 D1 Y1
0 1 0 D2 Y2
0 1 1 D3 Y3
1 0 0 D4 Y4
1 0 1 D5 Y5
1 1 0 D6 Y6
1 1 1 D7 Y7
PROCEDURE
1. Wire the circuit as per f igure above and verif y result f irst by giving clock signal to
One Input pin at a time of the IC (D0 – D1) and then to all the pins simultaneously.
Page | 59
TASK 6:
Page | 60
LAB ASSIGNMENT
1. Implement a Boolean Function with a MULTIPLEXER.
F(x,y,z) = Σ (1,2,6,7)
Page | 61
Page | 62
VERIFICATION OF LATCH AND FLIP FLOP OPERATION USING GATES AND
FLIP FLOP’S IC
1. Digital Logic Trainer.
2. IC 7402, 7400 , 7404 , 7410 , 7474 & 7475
Relevant Theory Topics: Synchronous Sequential Logic, Latches/Flip-flops (Refer

Chapter 05 Digital design, Edition by Morris Mano)
OBJECTIVE:
To learn about various types of Latches and Flip-Flops
THEORY:
a. A Flip Flop is a logic circuit that has two stable states Low or High. Enable
input signal may be used to enable or disable a f lip f lop. Clock signal is used
to synchronize operations of f lip f lops. Most (if not all) of the system output
can change state only when the clock makes a transition.
b. Latches are a f orm of Flip Flop, which do not require clock pulse to latch or
hold data present at its input.
Page | 63
TASK 1: SR (or RS or SC) Latch
The SR is the simplest f orm of Flip Flop or Latch. It can be constructed f rom NOR
gates or NAND gates. Standard logic symbol of SR f lip f lop and its truth table is given
below:-
NOR Gate SR Latch:
PROCEDURE
Wire the circuit as per f igure above and verif y the result.
NOTE: NAND Gate SR Latch has active low input, hence its truth table is dif f erent
f rom the standard i.e a low at the set terminal will set the latch.
Page | 64
TASK 2: GATED FLIP FLOPS
Gated SR Flip Flop :
Works only when Enable is high.
PROCEDURE
Gated D – Flip Flop :
PROCEDURE
Gated J-K Flip Flop
Page | 65
PROCEDURE
TASK 3: D-LATCH AND D-FLIP FLOP OPERATIONS
PROCEDURE
1. Wire the circuit as per f igure 1 & 2 above.

2. Connect +5V to V cc and Ground to pin GND of the ICs.
VERIFICATION – D LATCH:
1. Verif y that the data at the input
terminal is ref lected at the output
only when Enable (EN) input is high.
________________
2. Verif y that f or the duration that the Enable

input remains high, all changes in the data input
are ref lected at the output. ______________
Page | 66
VERIFICATION – D FLIP FLOP:
1. Verif y that the data at the input terminal is
ref lected at the output only during Positive
going edge of the Clock pulse._________
2. Verif y that the duration of the Clock

pulse has nothing to do with data
transf er in case of Flip Flop.
__________________
Page | 67
LAB ASSIGNMENT
1. Construct SR latch using NAND gates.
2. What changes would you make in the NAND gate latch shown above,
so it behaves exactly like a NOR gate S-R latch.
ANS.___________________________________________________
________________________________________________________
________________________________________________________
Page | 68
Page | 69
EE-220L Digital Logic Design LAB10
IMPLEMENTATION OF SEQUENTIAL CIRCUIT
Relevant Theory Topics: Analysis of clocked sequential circuits, State reduction and
assignment and Design procedure. (Refer Article 5.6, 5.7, Digital design, Edition by
Morris Mano)
INTRODUCTION:
In digital circuit theory, sequential logic is a type of logic circuit whose output
depends not only on the present input but also on the history of the input. This is in
contrast to combinational logic, whose output is a f unction of , and only of , the
present input. In other words, sequential logic has state (memory) while
combinational logic does not.
State diagram:
A state diagram is a type of diagram used in computer science and related f ields to
describe the behavior of systems. State diagrams require that the system described
is composed of a f inite number of states.
State table:
A state table is essentially a truth table in which some of the inputs are the current
state, and the outputs include the next state, along with other outputs.
There are two types of f inite state machine that can be built f rom sequential logic
circuits:
• Moore machine: the output depends only on the internal state. (The internal
state only changes on a clock edge; the output thus only changes on a clock
edge).
• Mealy machine: the output depends not only on the internal state, but also on
the inputs.
K-MAP:
A method f or minimizing a boolean expression, usually aided by a rectangular map of

the value of the expression f or all possible input values. Input values are arranged in
a Gray code. Maximal rectangular groups that cover the inputs where the expression
is true give a minimum implementation
CHOICE OF THE FLIP FLOP:

We can use any of the available f lip f lop f or our design depending upon the circuit
requirement. The design of a sequential circuit with f lip-f lops other than the D type is
complicated by the f act that the f lip-f lop input equations f or the circuit must be
derived indirectly f rom the state table. When D-type f lip-f lops are employed, the
input equations are obtained directly f rom the next state. This is not the case f or the
JK and other types of f lip-f lops. In order to determine the input equations f or these
f lip-f lops, it is necessary to derive a f unctional relationship between the state table
and the input equations.
Page | 70
Task 1:
Design a sequential circuit given by the lab instructor. And f ill the spaces.
1. State diagram
2. Reduced state diagram
3. State table
4. Flip f lop you are going to use and why?
5. Flip f lop input and output equations.
6. Logic diagram and simulation in PROTEOUS Sof tware.
Page | 71
Page | 72
Page | 73
Page | 74
IMPLEMENTATION OF SERIES AND PARALLEL REGISTERS
1. Digital Logic Trainer.
2. IC 7474 , 74166
Relevant Theory Topics: Shif t Registers (Ref er Chapter 06(6.1, 6.2), Digital
design, Edition by Morris Mano)

OBJECTIVE
To learn about various types of Registers.
THEORY:
a. A Register is simply a group of f lip-f lops that can be used to store a binary
number. Each f lip f lop of a register (called a cell) stores one bit of word. The
bits in a binary number (let’s call it data) can be moved f rom one place to
another in either of two ways. The f irst method involves shif ting the data 1 bit
at a time, in a serial f ashion, beginning with either MSB (most signif icant bit)
or LSB (least signif icant bit). This technique is known as serial shifting. The
second method involves shif ting all the data bits simultaneously and is ref erred
to as parallel shif ting.
b. There are two ways of shif ting data into a register (serial or parallel) and
similarly two ways to shif t data out of the register. It is theref ore possible to
construct f our basic types of registers as shown below:
Serial-in Serial-out Serial-in Parallel-out
Page | 75
Parallel-in Parallel-out Parallel-in Serial-out

TASK 1: SERIAL-IN SERIAL-OUT SHIFT REGISTER
The Serial-in Serial-out register accepts data serially that is one bit at a time on a
single line. It produces the stored inf ormation on its output in serial f orm. The f igure
below shows a 4-bit Serial-in Serial-out shif t register. It is called 4-bit shif t register
because it has 4-places to store data A,B,C& D.
Inputs Data Out

Preset Clear Clock
D Q Q’
PR CLR CLK
L H X X H
H L X X L
L L X X H
H H ↑ H H
Functional Table of
H H ↑ L L
H H L X QO
IC 7474
Pin Configuration IC 7474
PROCEDURE
Wire the circuit as per f igure above and complete the table below.
Page | 76
Data Out
Clock
Data In FF
Pulse
D
0 0
1(LSB) 1
1 2
1 3
1 4
0 5
0 6
1 7
1(MSB) 8
- 9
- 10
- 11
- 12
TASK 2: SERIAL-IN PARALLEL-OUT SHIFT REGISTER

The Serial-in Parallel-out register accepts data serially that is one bit at a time on a
single line. It produces the stored inf ormation on its output in parallel f orm. The
f igure below shows a 4-bit Serial-in Parallel-out shif t register.
Page | 77
Data
Clock Pulse Data In
Out
1 1 (LSB)
2 0
3 1
4 1 (MSB)
Af ter 4th pulse, immediately
disconnect Clock Input to see
desired output displayed (and -
latched/held indef initely) by the
LEDs
Table 2
PROCEDURE
Wire the circuit as per f igure above and write your observation.
TASK 3: PARALLEL-IN PARALLEL-OUT SHIFT REGISTER

The Parallel-in Parallel-out register accepts data in parallel manner that is all bits at a
time on parallel lines. It also produces the inf ormation on its output in parallel f orm.
The f igure below shows a 4-bit Parallel-in Parallel-out shif t register.
Page | 78
Data In Clock Data Out
PROCEDURE
Wire the circuit as per f igure above and write your observations.
TASK 4: PARALLEL-IN SERIAL-OUT SHIFT REGISTER

The Parallel-in Serial-out register accepts data in parallel manner that is all bits at a
time on parallel lines. It however produces the inf ormation on its output in serial
f orm.
IC 74166, shown below is shif t register. It can shif t either Serial or Parallel data
entry or it outputs Serial data. In this experiment we will use Parallel input and
Serial Output capabilities of the IC Pin 15 is Shif t
and Load pin. When it is LOW, the register loads
d ata. It is HIGH, the register outputs data.
CONNECTION:
1. Do not connect Pin 1 (it is f or serial input)
2. Connect inputs A,B,C,D,E,F,G,H to switches S0 to S7.
3. Connect Clock Inhibit Pin 6 to Ground.
4. Connect Clock Pulse to pin 7 and also to LED L8 (f or counting clock pulse)
5. Connect Output QH to LED L0
6. Connect a long wire to the IC pin 15 and keep other terminal of the wire
hanging (due to limited number of switches in the trainer, we will manually
connect this end of the wire to ground for data loading and keep it free
(or High)f or data shifting)
7. Connect Vcc and GND.
Page | 79
PROCEDURE
Wire the circuit as per f igure above. Select various combination of inputs. Load the
input and then shif t it to output. Observe output (the state of the LED when data is
loaded shows state of pin H).
Page | 80
LAB ASSIGNMENT
1. Can you make necessary changes so that above register becomes a Circular
Shift Register?
Page | 81
Page | 82
IMPLEMENTATION OF ASYNCHRONOUS AND SYNCHRONOU S COUNTERS
2. IC 7473, IC 74192, 7400 & 7408
Relevant Theory Topics: Ripple counters, Synchronous counters and Johnson

counter (Ref er Chapter 06Digital design, Edition by Morris Mano)
OBJECTIVE:
To learn about Asynchronous and Synchronous Counters.
THEORY:
a. A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter. They are used f or counting the
number of occurrences of an event and are usef ul f or generating timing
sequences to control operations in a digital system.
b. A counter that f ollows the binary sequence is called binary counter.
c. An N bit binary counter consists of n f lip-f lop and can count in binary f rom 0 to
2N -1.
d. In an asynchronous counter, the output of one FF (Flip-Flop) drives the CLK
(Clock) input of the next FF.
e. In a synchronous counter (or parallel counter) all the FFs are triggered
simultaneously by the clock pulse.
TASK1: FOUR BIT (OR MOD 16) COUNTER

The basic asynchronous counter is limited to MOD numbers that are equal to 2 N,
where N is the number of FFs. In case of 4 Bit Counters, we have to use 4 FFs. The
counter in this case will count up to 15.
Circuit Diagram - Counter
Page | 83
PROCEDURE
Wire the circuit as per f igure above and verif y the counter is counting a binary
sequence. Also plot the timing diagram.
Pin Conf iguration IC 7473
TASK2: MOD 10 COUNTER

The counting sequence of mod-10 counter is f rom 0000 to 1001 (0 to 9 decimal)
Page | 84
PROCEDURE
Wire the circuit as per f igure above and verif y the counter is counting upto 9.
TASK 3: 3-BIT SYNCHRONOUS COUNTER

The counting sequence of 3 bit (mod-8) counter is f rom 000 to 111 (0 to 7 decimal)
PROCEDURE
Wire the circuit as per f igure above and verif y the counter is counting upto 7.
Page | 85
TASK 4: SYNCHRONOUS DECADE UP/DOWN COUNTER
IC 74192 is a Synchronous Decade up/down counter. Circuit diagram is as shown
below.
PROCEDURE
Wire the circuit as per f igure above and verif y the counter is counting up or down
as desired.
Page | 86
Page | 87
IMPLEMENTATION OF RAM AND ROM
2. 7402, 7404, 7408, and 7493.
Relevant Theory Topics: Memory and Programming logic RAM,ROM,PLA,PAL
(Ref er Chapter 07Digital design, Edition by Morris Mano)
OBJECTIVE:
To learn about various types of Memories.
THEORY:
a.A semi-conductor memory is an integrated circuit , capable of storing a binary
number. Generally speaking, memory elements can be divided into two
categories. One is called Random Access Memory (RAM), and the other is
called Read Only Memory (ROM). RAM is where we store Code and Data so
that CPU can work on it. It is Volatile memory that means that when power is
turned of f , the contents of the memory is cleared. ROM, on the other hand
retains data stored in it.
b. RAM circuits on the market have dif f erent conf iguration depending on how the
memory cell array is organized. A memory cell array organized with N by M
cells (N x M) can store N words with each word having M bits. So a 8K x 8 RAM
(IC 6116) can store 8K words, each word having 8 bits in it.
TASK 1 : DESIGN OF A MEMORY CELL

Flip-Flop f orms the basic “memory cell” in semiconductor memories. We will verif y that
a memory cell made of SR f lip f lop perf orms basic f unctions of writing data into the
Page | 88
cell and Reading data out of it.
PROCEDURE
1. Connect the circuit as shown above.

2. Input the data to be written (0 or 1) with the help of Input Switch.
3. Write data into the f lip-f lop by putting Write Enable switch to LOW.
4. Now that data has been written into the f lip f lop, put the Write Enable switch
to High.
5. Put the Out Enable (Read) switch to HIGH to read the data written in the cell.
The LED should be on or of f depending on what data has been written in.
6. Verif y that the data written once, does not change unless a f r esh data is
written in the cell.
TASK2: WORKING WITH 8K X 8 RAM IC

The 6116 IC is a 16K (actually 16,384) bit high-speed CMOS Static RAM organized
as 2K. It has 11 Address Input pins (so it can address 211 = 2056 addresses).
Similarly it has 8 Data Input/output pins (hence each data word can have 8 bits)
Page | 89
Page | 90
Digital Logic Design LAB 14
IMPLEMENTATION OF LAMP HAND BALL GAME
OBJECTIVE:
In this experiment, you will construct an electronic game of handball using a single
light to simulate the moving ball. This project demonstrates the application of bi-
directional shif t register with parallel load. It also shows the asynchronous input of
f lip-f lops. We will f irst introduce an IC that ins needed f or this experiment and then
present the logic diagram of the simulated lamp handball game.
Relevant Theory Topics: Latches and Flip f lop (Ref er Chapter 05Digital design,
Edition by Morris Mano)
IC Type 74194:
The pin assignment to the inputs and outputs is show in f ig A. The two mode control
inputs determine the type of operations as specif ied in the f unction table.
Logic Diagram:
The logic diagram of the electronic lamp handball is shown in f ig b. It consists of two
74194 IC’s, a dual D f lip f lop 7474IC,and three gate ICs:7400,7404 and 7408.The
ball is simulated by moving light that is shif ted lef t or right through the bidirectional
shif t register. The rate at which the light moves is determined by the f requency of
the clock. The circuit is f irst initialized with the reset switch. The start switch starts
the game by placing the ball (an indicator lamp) at the extreme right. The player
must press the pulser push button to start the ball moving to the lef t. The single
light shif ts to the lef t until it reaches the lef tmost position (the wall), at which the
ball returns to the player by reversing the direction of shif t of the moving light. When
the light is again at the rightmost position, the player must press the pulser again to
reverse the direction of shif t. If the player presses the pulser too soon or too late,
the ball disappears and the light goes of f . The game can be restarted by returning
the start switch on and then of f . The start switch must be open (logic -1) during the
game.
Page | 91
FIGURE A
Circuit Analysis:
Prior to connecting the circuit, analyze the logic diagram to ensure that you
understand how the circuit operates. In particular, try to answe r the f ollowing
questions:
1. What is the f unction of the reset switch?
2. Explain how the light in the rightmost position comes on when the start
switch is grounded. Why it is necessary to place the start switch in the logic -1
position bef ore the game starts?
3. What happens to the two mode-control inputs, S1 and S0, once the ball is set
in motion?
Page | 92
4. What happens to the mode-control inputs and to the ball if the pulser is
pressed while the ball is moving to the lef t? What happens if it is moving to
the right but has not reached the rightmost position yet?
5. Suppose that the ball returned to the rightmost position, but the pulser has
not been pressed yet; what is the state of the mode-control inputs if the
pulser is pressed? What happens if it is not pressed?
FIGURE B
Page | 93
Playing the Game:
Wire the circuit of Fig. B. Test the circuit f or proper operation by playing the game.
Note that the pulser must provide a positive-edge transition and that both the reset
and start switches must be open (be in the logic-1 state) during the game. Start with
a low clock rate and increase the clock f requency to make the handball game more
challenging.
Counting the number of losses:

Design a circuit that keeps score of the number of times the player losses
while playing the game. Use a BCD-to-seven-segment decoder and a seven-segment
display as in Fig. c to display the count f rom 0 to 9. Counting is done with a decimal
counter using either the 7493 as a ripple decimal counter or the 74161 and a NAND
gate as a synchronous decimal counter. The display should show 0 when the circuit
is reset. Every time the ball disappears and the light goes of f , the display should
increase by 1. If the light stays on during the play, the number in the display should
not change. The f inal design should be an automatic scoring circuit, with the decimal
display incremental automatically each time the player losses when the light
disappears.
Page | 94
LAB ASSIGNMENT:
Lamp Ping-Pong:
Modif y the circuit of Fig. b so as to obtain a lamp Ping-Pong game. Two players can
participate in this game, with each player having his own pulser. The player with the
right pulser returns the balls when in the extreme lef t position, and the player with
the lef t pulser returns the ball when in the extreme lef t position. The only
modif ication required f or the Ping-Pong game is a second pulser and a change of f ew
wires.
With a second start circuit, the game can be made to start (serve) by either
one of the two players. This addition is optional.
Page | 95
Page | 96

EE220L DLD Lab Manual Fall 2022

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EE220L DLD Lab Manual Fall 2022

Uploaded by

Copyright:

Available Formats

Digital Logic Design Lab

University of Management & Technology

University of Management and Technology

Duration One semester

Resource Persons M. Asad Ali (A1,A2)

Counseling Timing See Office Window

• To practically know and perform the digital logic design concepts

Grade Evaluation Criteria:

Lab Manuals & Performance: 50

Final Viva + Performance: 20 + 20

Course Learning Outcomes (CLOs):

Relation to EE Program Learning Outcomes (PLOs):

Calendar of Course contents to be covered during semester

Course Code: EE-220L Course title: Digital Logic Design Lab

2 Universality of NAND and NOR gates TB: Article 3.7 1,2,3,4

Implementation of Multiplexer and Demultiplexer

11 Implementation of Sequential Circuits TB: Article 5.8 1,2,3,4

16 Term Project Evaluation All concepts 1,2,3,4,5

Complex Engineering Problem/Activity:

Complex Engineering Problem Included: No

Complex Engineering Activity Included: No

VERIFICATION OF BASIC BINARY OPERATORS AND BASIC THEOREMS

TASK 1: LOGICAL “AND” OPERATION

Symbol of AND gate Truth Table for AND operation

1. Insert the IC 7408 on the trainer’s breadboard.

TASK 3: VERIFICATION OF ABSORPTION THEOREM

 Verif y Absorption Theorem A + (A . B) = A

 Draw Circuit Diagram.

 Draw Circuit Diagram.

1. What kind of logic operation does this chip perform?

TASK 1: NAND GATE IMPLEMENTATION OF BOOLEAN FUNCTIONS

Figure 2a: AND gate operation

Figure 2b: OR gate operation

Figure 2c: NOT gate operation

1. Insert the IC on the trainer’s breadboard.

 Verif y OR gate operation using NAND gates (See Fig. 2b).

TASK 2: ALTERNATE LOGIC GATE REPRESENTATION

It is becoming increasingly more common to use alternate logic symbols in logical

Above mentioned alternate logic gate is equivalent to _________ gate.

Above mentioned alternate logic gate is equivalent to _________ gate.

Above mentioned alternate logic gate is equivalent to _________ gate.

(1) Digital Logic Trainer

Relevant Theory Topics: Adder/ Subtractor (Refer to Chapter 04 Digital design,

1. To learn Half and Full Adder Operations.

TASK 1: HALF ADDER.

Table 1: Truth Table f or Half Adder operation

Figure 1: Half Adder using AND and XOR gates.

1. Wire the circuit as per f igure 1 above.

TASK 2: FULL ADDER.

Cout = (A B) Cin + A.B

Figure 2: Full Adder comprising of two Half Adders and an OR gate.

1. Wire the circuit as per f igure 2 above.

Figure 3: IC 74283 Internal Functional Structure

Figure 4: Connection Diagram f or 4-Bit Parallel Adder

1. Wire the circuit as per f igure 4 above.

Inputs Desired Output Observed Output

Relevant Theory Topics: Design of combinational logic Adder/ Subtractor (Refer to

Posn 4 Posn 3 Posn 2 Posn 1 Posn 0

The possible combinations f or f ull subtraction would be;

Implement Full Subtractor

Figure : Connection Diagram f or IC 74283

DECIMAL BCD GRAY CODE EXCESS-3 CODE

TASK 1: BCD TO SEVEN SEGMENT DISPLAY CODE CONVERSION

Figure 1: BCD to Seven Segment Converter Circuit.