Training Document

For
SYNTHESIS IN BACK-END VLSI DESIGN
By
Mirafra Technologies, Bangalore

Sr. No. CONTENT Page No.

1 Introduction 02
2 Input files required 04
3 Synthesis Flow in Various tools 05
4 Steps in Synthesis 07
4.1 Analyze 07
4.2 Elaborate 07
4.3 Import constraints and UPF 08
4.3.1 SDC Contents: 08
4.4 Clock gating 14
4.5 Compile 16
4.6 Optimization 16
4.7 DFT (Design for Testing) insertion 17
4.8 Compile incremental 18
4.9 Outputs of Synthesis 18
4.10 4.10 Checklist 18
5 Synthesis Command 20

6 Synthesis Script - Physical Aware 21

7 Reports & Outputs 22

8 Basic Training Videos 23

Prepared by: Amol K. Boke,

PD Trainer at Mirafra Technologies, Bangalore

1. INTRODUCTION

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Synthesis is process of converting RTL (Synthesizable Verilog code) to technology

specific gate level netlist (includes nets, sequential and combinational cells and their

connectivity).

1.1 Synthesis Transformation Process:

1. Translate

 Process of converting RTL to equation format

 Basic Boolean optimization is carried out to reduce the literals

 Completely independent code is converted to tool dependent.

2. Map

 The obtained equations are directly mapped to the technology library

 Named technology / library binding

 Become design is bound to particular tool as well as technology

3. Optimize

 Technology mapped design is optimized to meet the specifications

 Various timing algorithms and architectures are involved to meet the

specifications

 Design is primarily optimized to meet timing specifications

1.2 Goals of Synthesis

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 To get a gate level netlist

 Inserting clock gates

 Logic optimization

 Inserting DFT logic

 Logic equivalence between RTL and netlist should be maintained

2. INPUT FILES REQUIRED

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 1. Technology related:

 Target Library

 The target library is the

technology library you want to

map to during synthesis. It is

also known as the destination

library.

 Specify the target library with

the pointer variable

target_library.

 Link Library

 The link library is a technology

library that is used to describe

the function of mapped cells Fig 1. Inputs and outputs in Synthesis Flow

prior to optimization.

 Specify the link library with the variable pointer link_library.

 Typically, the link and target library are set to the same technology library.

 The first entry in the list should be "*" to use designs currently in memory.

 .lib-timing info of standard cell & macros

2. Design related:

 .v- RTL code.

 SDC- Timing constraints.

 UPF- power intent of the design.

 Scan config- Scan related info like scan chain length, scan IO, which flops are to be

considered in the scan chains.

3. Physical aware related:

 RC co-efficient file (tluplus).

 LEF/FRAM- abstract view of the cell.

 Floorplan DEF- locations of IO ports and macros.

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3. SYNTHESIS FLOW IN VARIOUS TOOLS

Fig. 2: Synthesis Flow in Genus

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Fig. 3: Synthesis Flow in DC

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 3. STEPS IN SYNTHESIS

Fig4: Steps in Synthesis

4.1 Analyze

 Checks syntax on RTL and generates immediate files.

4.2 Elaborate

 Brings all lower level blocks into synthesis tool.

 All the codes and arithmetic operators are converted into Gtech and DW (Design

Ware) components. These are technology independent libraries.

 Gtech- contains basic logic gates &flops.

 DesignWare- contains complex cells like FIFO, counters.

 Elaborate performs following tasks;

 Analyses design hierarchy.

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 Removes empty switches and dead branches.

 Executes initial commands.

 Detects asynchronous reset.

 Converts decision trees to mux.

 Converts synchronous to Dlatch/DFF.

 FSM pass

 Detects FSM logic and extracts the no of input, output bits and state bits.

 Converts FSM logic to basic logic.

 Memory pass

 Merging DFF to memory write(memwr) and memory read (memrd)

 Consolidating memwr/memrd cells

 Generate memory (mem) cells

 Mapping mem cells to basic logic

4.3 Import constraints and UPF

If the design consists of multiple power domains, then using the UPF power domains,

isolation cells, level shifters, power switches, retention flops are placed.

Once the design is extracted in the form of technology independent cells, timing

constraints are imported from the SDC file.

4.3.1 SDC Contents:

Timing Constraints:

 Clock Definition(Time period, Dutycycle)

Timing Exceptions:

 False paths, Asynchronous paths

Non-Timing Constraints:

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  Operating conditions(PVT)

 Wire load models

 System Interface

 Design rule constraints

 Area Constraints

 Multi voltage and power optimization constraints

4.3.1.1 Header Type:

1. SDC Version:

• This statement specifies the version of the SDC file. it could be 2.1, 2.0, 1.9 or

more older.

• Version 2.1 has introduced in December 2017.

Example: 
• set sdc_version 2.1

2. Units:

• Units of various quantities like time, resistance, capacitance, voltage, current,

and power can be specified using set_unit command.

• Multiples units can be set using a single set_unit command.

4.3.1.2. Clock Definition:

To define a clock we need to provide the following information:

i)clock source

ii)Period

iii)Duty cycle

iv)Edge Times

Syntax:
create_clock [-name clock_name] [clock_sources] [-period value] [-waveform
edge_list] [-add] [-comment] 

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Example:

create_clock "u13/z" -name "CLK" -period 30 -waveform {12.0 27.0}

4.3.1.3 Generated clock:

A Generated clock is a clock derived from a master clock. A master clock is a clock

defined using the create_clock specification.  A pin or port could be specified for the

generated clock object. Generated clock follow the master clock, so whenever the

master clock changes generated clock will change automatically. A generated clock can

be created as a frequency-divided clock,  a frequency multiplied clock, an edge divided

clock or an inverted clock

Syntax:

create_generated_clock [-name clock_name] [-add] source_objects -source

master_pin [-master_clock clock] [-divide_by divide_factor | -multiply_by
multiply_factor ] [-duty_cycle percent] [-invert] [-preinvert] [-edges
edge_list] [-edge_shift edge_shift_list] [-combinational]

Group path:

Syntax:
group_path [-weight weight_value] [-critical_range range_value] -default |
-name group_name [-from from_list | -rise_from rise_from_list | -fall_from
fall_from_list] [-through trough_list | -rise_through rise_through_list -
fall_through fall_through_list] [-to to_list | -rise_to rise_to_list | -
fall_to fall_to_list] [-comment comment_string] [-priority priority_level]
Example: group_path -name "group1" -weight 2.0 -to {CLK1A CLK1B}

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Clock uncertainty:

Syntax:

set_clock_uncertainity [object_list | -from from_clock | -rise_from

rise_from_clock | -fall_from fall_from_clock -to to_clock | -rise_to
rise_to_clock | -fall_to fall_to_clock] [rise] [-fall] [-setup] [-hold]
uncertainty 

Example: set_clock_uncertainty -setup 0.5 [get_clocks clk1]

set_clock_uncertainty -hold 0.2 [get_clocks clk1]

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4.3.1.4 Clock latency:

Syntax:

set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-early] [-late]

[-dynamic jitter] [-clock clock_list] delay object_list

Input delay:

Syntax:

set_input_delay delay_value [-reference_pin pin_port_name] [-clock

clock_name] [-level_sensitive] [-network_latency_included] [-source-
latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] port_pin_list

Example:

set_input_delay -max 1.35 -clock clk1 {ain bin} 

Output delay:

Syntax:

set_output_delay delay_value [-reference_pin pin_port_name] [-clock

clock_name] [-clock_fall] [-level_sensitive] [-network_latency_included]
[-source-latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] [-
group_path group_name] port_pin_list

Example:

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set_output_delay 1.7 -clock [get_clocks CLK1] [all_outputs]

4.3.1.5 Timing Exceptions:

a. False path:

• False path is nothing but logic does not exists.

• It is possible that certain timing paths are not real (or not possible) in the

actual functional operation of the design. Such paths can be turned off during

STA by setting these as false paths. A false path is ignored by the STA for

analysis.

For example, When a false path is specified through a pin of a cell, all paths that go

through that pin are ignored for timing analysis. The advantage of identifying the false

paths is that the analysis space is reduced, thereby allowing the analysis to focus only

on the real paths.

Example: set_false_path -from [souce ] -to [destination ]

b. Multi cycle path:

• In some cases, the combinational data path between two flip-flops can take

more than one clock cycle to propagate through the logic. In such cases, the

combinational path is declared as a multicycle path.

• Even though the data is being captured by the capture flip-flop on every clock

edge, we direct STA that the relevant capture edge occurs after the specified

number of clock cycles.

Example: set_multicycle_path 2 -from A -to B 

c. Max Delay and Min Delay:

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 • The path groups are of four types: input-to-reg, reg-to-output, reg-to-reg and

input-to-output.

• we have to constrain these paths to maximum delay or minimum

delay. set_max_delay and set_min_delay commands are used to define these

delays.

Example:  set_max_delay 0.15 -from IO8 -to IO9

4.4 Clock gating

Due to high switching activity of clock a lot of dynamic power is consumed. One of the

techniques to lower the dynamic power is clock gating. In load enabled flops, the output

of the flops switches only when the enable is on. But clock switches continuously,

increasing the dynamic power consumption.

By converting load enable circuits to clock gating circuit dynamic power can be reduced.

Normal clock gating circuit consists of an AND gate in the clock path with one input as

enable. But when enable becomes one in between positive level of the clock a glitch is

obtained.

Fig. 5: Load enabled register bank

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 Fig. 6: Clock gated register bank

Fig. 7: Waveform for clock gate

To remove the glitches due to AND gate, integrated clock gate is used. It has a

negative triggered latch and an AND gate.

Fig. 8: Integrated clock gated register bank

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 Fig. 9: Waveform for ICG

Clock gating makes design more complex. Timing and CG timing closure becomes

complex. Clock gating adds more gates to the design. Hence min bit width (minimum

register bit width to be clock gated) should be wisely chosen, because the overall

dynamic power consumption may increase.

4.5 Compile

 Performs Boolean optimization.

 Maps all the cells to technology libraries.

 Performs logic and design optimization.

4.6 Optimization
 Logic optimization

 Constant folding

 Detect identical cells

 Optimize mux(dead branches in mux)

 consolidate mux and reduce inputs(many to single)

 Remove DFF with constant value

 Reduce word size of the cells

 Remove unused cells and wires

 Design optimization

 Reduce TNS and WNS

 Power Optimization

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 Area Optimization

 Meet the timing DRV’s

 incremental clock gating

4.7 DFT (Design for Testing) insertion

 DFT circuits are used for testing each and every node in the design.

 More the numbers of nodes that can be tested with some targeted pattern, more is the

coverage.

 To get more coverage the design needs to be more controllable and observable.

 For the design to be more controllable we need more control points (mux through which

alternate path is provided to propagate pattern).

 For the design to be more observable we need more observe point (A scan-able flop

that observes the value at that node).

 Scan mode is used to test stuck at faults and manufactured devices for delay.

 Scan mode is done using scan chains

 Scan chains are part of scan based designs to propagate the test data.

 By having scan chains, the design can be more controlable and observable.

 Each scan chain inputs the pattern through scan input and outputs the pattern through

scan output.

 Scan chain consists of scan flops where the output of scanflops is directly connected

to scan inputs of the flops.

 Stages of scan mode

 Inputs the pattern through scan input port.

 Scan shift- Scan enable is set to 1. Then inputs the pattern through the scan input,

shifts the pattern through the scan flops and load all the flops with test pattern.

 Scan capture- Scan enable is set to 0. In one clock cycle the loaded value in the flops

propagates through combinational circuit and reaches the D pin of the next flop.

 Scan enable is set to 1 and outputs the pattern through scan output port.

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 The scan chain length and number of scan chains has to be properly chosen, as having

more scan chain length increases the pattern propagation time and having more scan

chains increases the number of scan IO ports.

Fig7: Scan chain

4.11 Compile incremental

 Technology mapping of DFT circuit

 Optimization of the design

4.12 Outputs of Synthesis

 netlist

 SDC

 UPF

 ScanDEF- information of scan flops and their connectivity in a scan chain

4.13 Checklist

 Check if the RTL and netlist are logically equivalent (LEC/FM).

 Check if SDC and UPF are generated after synthesis and also check their

completeness.

 Check if there are any assign statements.

 Checks related to timing

 Combinational loops

 Un-clocked registers

 unconstrained IO’s

 IO delay missing

 Un-expandable clocks

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 Master slave separation

 multiple clocks

 Checks related to design

 Floating pins

 multi driven inputs

 un-driven inputs

 un-driven outputs

 normal cells in clock path

 pin direction mismatch

 don’t use cells

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 4. SYNTHESIS COMMAND

Genus:-

 set_db init_lib_search_path pathname

 read_libs {libName}
 set_db init_hdl_search_path hdlPath
 read_hdl rtl_fileNames
 set_design_mode -process 65
 set_db lp_insert_clock_gating true
 Elaborate
 check_design –all
 read_sdc sdc_filename
 check_timing_intent
 uniquify -verbose [current_design]
 set_db wireload_selection none
 set_wire_load_selection_group group_name
"design:top_module_name" .force_wireload wirelaod_name
 syn_generic
 syn_map
 set_db leakage_power_effort high
 syn_opt ;incremental

Design Compiler (DC):-

 set_app_var target_library “name”

 set_app_var symbol_library “name”
 set_app_var link_library “* $target_library ”
 set_app_var search_path “”
 read_file –format verilog rtlFile.v / read_verilog rtlFile.v
 check_library
 analyze
 elaborate topModuleName
 link
 uniquify
 check_design
 read_sdc sdcFileName.sdc
 set auto_wire_load_selection true
 compile_ultra

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 5. SYNTHESIS SCRIPT - PHYSICAL AWARE

Genus Physical:-

 set_db / .init_lib_search_path path

 set_db / .init_hdl_search_path path
 read_libs libname
 read_physical -lef lef file(s)
 set_db / .cap_table_file file / read_qrc qrcTechFile name
 set_db / .congestion_effort low|medium|high
 read_hdl hdl file name(s)
 elaborate
 read_sdc file_name
 read_def file_name -> floorplan DEF
 syn_generic –physical
 syn_map –physical
 syn_opt –physical

Design Compiler (Topo):-

 set_app_var target_library “name”

 set_app_var symbol_library “name”
 set_app_var link_library “* $target_library ”
 set_app_var search_path “”
 create_mw_lib –technology –mw_reference_library
 open_mw_lib -technology
 check_library
 Set_tlu_plus_file –max_tluplus –min_tluplus –tech2itf_map
 check_tlu_plus_files
 analyze –format Verilog “rtlFileName.v”
 elaborate topModuleName
 link
 check_design
 read_sdc sdcFileName.sdc
 extract_physical_constraints filename.def
 compile_ultra

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 6. Reports & outputs

Genus

 Reports:-
o report_area
o report_gates
o report_power
o report_timing
o report_qor
 Outputs:-
o write_hdl
o write_sdc
o write_sdf

Design Compiler

 Reports:-
o report_area
o report_power
o report_timing
 Outputs:-
o write –format ddc –output topName.ddc  contains both netlist and
constraints
o write –f Verilog –output tModuleName.v
o write_sdf topModuleName.sdf
o write_sdc topModuleName.sdc

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 7. BASIC TRAINING VIDEOS

For Beginners

1) Synthesis Basics By Yugesh

https://web.microsoftstream.com/video/8906f8d6-f3c0-4f4d-8928-
8b36e6cfe06c?channelId=4561001b-716f-4cf7-9f4b-c5d545f5d02d

2) SDC basics - Sravya

https://web.microsoftstream.com/video/430caf57-81a8-4104-aeb6-
8db24d6a0566

3) SDC Concepts by Yugesh

https://web.microsoftstream.com/video/d6098bd4-86c1-428e-9033-
7263e683ce0c

4) SDC file format by Bharathi B

https://web.microsoftstream.com/video/d85765ee-afd0-43ef-aec1-
d2d97e266a0f

5) DC lab Discussion (Synthesis Basics Part 2) by Yugesh

https://web.microsoftstream.com/video/596143cb-373f-410c-bab2-
53560e171e18

6) Synthesis Commands - Sai Nandan

https://web.microsoftstream.com/video/b1c8d2f5-bf51-4633-9d56-
f4565b956cfc

7) Synthesis Signoff and QC checks - Dominic

https://web.microsoftstream.com/video/76c9017c-d728-4033-a3db-
42c157ada578

8) Synthesis_DClab_20210308_by tarak
https://web.microsoftstream.com/video/78fef134-52c0-4070-9e19-
1915c2bbfd24

9) Synthesis_genus_basic flow by sonal_20210315

https://web.microsoftstream.com/video/bc355a81-530b-4352-babc-
4218ae962d07

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Moderate training videos:

1) Synthesis Challenges - Vamsi Krishna

https://web.microsoftstream.com/video/e99b0339-55cd-4847-b581-
08ccf51afe97?channelId=4561001b-716f-4cf7-9f4b-c5d545f5d02d

2) Synthesis _ Fusion Compiler

https://web.microsoftstream.com/video/54739d0a-b8cf-435d-826e-
b809db837432

3) Interaction and Knowledge sharing session from Kumar KJ - Synthesis and

Timing analysis
https://web.microsoftstream.com/video/c9ca39bd-9cb4-4eae-9c88-
3e0ce2016c33

4) Synthesis, LEC _ CLP Discussion

https://web.microsoftstream.com/video/a7b564b9-2760-40a9-ab3d-
c81804ff525b

5) Synthesis, LEC _ CLP Discussion _ follow up

https://web.microsoftstream.com/video/5bbcf0aa-c544-4eb8-819c-
65a1de7c2022

Advanced training videos:

1) Synthesis In FC (part 1) by Sushil

https://web.microsoftstream.com/video/158c0297-4f9f-449a-a2b7-
7c76edd82f8d

2) Synthesis In FC (part 2) by Manjunath and Aditi

https://web.microsoftstream.com/video/bf4d1d21-e4cd-4f54-8607-
0a0e53286aa4

3) Synthesis_genus overveiwflow by gavendra

https://web.microsoftstream.com/video/25575434-6458-4389-98a9-
aad906a85f92

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