GOVERNMENT COLLEGE OF ENGINEERING,

TIRUNELVELI

EC 3561 – VLSI LABORATORY

Name :

Register Number :

Degree & Department : B.E & ECE

Regulation : 2021

Year & Semester : III Year & V Semester

 GOVERNMENT COLLEGE OF ENGINEERING,
TIRUNELVELI-627007

DEPARTMENT OF ECE
2023-2024

REGISTER NUMBER:

CERTIFICATE

This is a Bonafide record of work done

by..................................................................... EC3561 – VLSI Laboratory,
Government College of Engineering, Tirunelveli during the year 2023-2024.
STATION: TIRUNELVELI – 7

DATE:

Staff-In-Charge Head Of The Department

Submitted for the Anna University Practical Examination held at Government College of
Engineering, Tirunelveli on.....................................................................................................

INTERNAL EXAMINER EXTERNAL EXAMINER

S.NO DATE Name of The Experiment Marks Signature

1 Study of design flow and FPGA architecture

2a Design, simulation and implementation of basic

combinational circuits (mux & demux)
2b Design, simulation and implementation of
Sequential circuits (flip-flop)
3a Design, simulation and implementation of Adder

3b Design, simulation and implementation of

Multiplier
4 Design, simulation and implementation of
Universal shift register
5 Design, simulation and implementation of
Memories
6 Design, simulation and implementation of Finite
state Machine
7 Design, simulation and implementation of
Synchronous Up/Down Counter
8 Design, simulation and implementation of
Asynchronous Up/Down Counter
9a Design and simulation of CMOS basic Gates
(Manual and automatic)
9b Design and simulation of Flipflops
(Manual and automatic)
10 Design and simulation of Synchronous Counter
(Manual and automatic)
11 Study of Tanner Tool
12 Design and simulation of CMOS Inverting
Amplifier
13 Design and simulation of basic CMOS amplifier
circuits (CS, CD & CG Configurations)
14 Design and simulation of Five Transistor
Differential amplifier
EX.NO: 1 STUDY OF DESIGN FLOW AND FPGA
DATE: ARCHITECTURE

AIM:
To study the VLSI Design Flow and FPGA Architecture.

THEORY:
VERILOG:
Verilog HDL is one of the two most common Hardware Description Languages
(HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDLs allows the
design to be simulated earlier in the design cycle in order to correct errors or experiment with
different architectures. Designs described in HDL are technology-independent, easy to
design and debug, and are usually more readable than schematics, particularly for large
circuits. Verilog can be used to describe designs at four levels of abstraction:
(i) Algorithmic level (much like c code with if, case and loop statements).
(ii) Register transfer level (RTL uses registers connected by Boolean equations).
(iii) Gate level (interconnected AND, NOR etc.).
(iv) Switch level (the switches are MOS transistors inside gates).

The language also defines constructs that can be used to control the input and output
of simulation.
DESIGN AND TOOL FLOW:
For designing digital systems using programmable logic devices (PLDs), such as
FPGA devices (Spartan families), computer aided design (CAD) software packages (Xilinx
ISE 9.2i) are used. These software packages assist the designer through all the stages of the
design process. Therefore, most of the CAD packages for programmable logic devices
provide the following main functions:
DESCRIPTION OF THE DIGITAL SYSTEM:
 Synthesis of the description, which means transforming the description into a
netlist containing basic logic gates and their interconnections;
 Functional simulation of the system based on the netlist obtained, before the
implementation in a specific device;
 Implementation of the system in a device, by adapting the netlist for an efficient
usage of the device’s available resources;
 Configuration (programming) of the device in order to perform the desired
function.
WORKING FUNCTION:
System Description: During the design entry you will describe your FPGA design with a
high-level hardware description language. In this lab course we will use Verilog for this
purpose.
Behavioural Simulation: The behavioural simulation is the most important step in verifying
the correct functionality of your circuit description. First the simulator compiles your Verilog
files and indicates syntax errors. If the compilation runs without errors, the behaviour of the
circuit design can be investigated in a waveform showing signal traces of external and
internal signals.
Synthesis, Place & Route: During the synthesis step your Verilog circuit description is
analysed by the synthesis tool and transformed into a gate-level netlist. The netlist elements
can then be placed on the FPGA’s configurable cells and connected by suitable interconnect
lines. Finally, a bitstream file is generated containing the configuration information for the
FPGA.
Post-layout Simulation: The post-layout simulation is performed on the netlist generated in
the synthesis step. Additionally timing information, which are provided by the Place &
Route-tool can be used for simulating the final circuit with correct signal timings. A post-
layout simulation is useful for resolving timing problems in your circuit. For simple FPGA
designs this type of simulation is usually not necessary.
Download: The download transfers the bitstream data to the target board for configuring the
FPGA.
Test & HW Debugging: Finally, the configured FPGA can be tested. In some cases it might
be necessary to attach a logic analyser to the FPGA for verifying the correct functionality of
the HW circuit or for debugging errors, which cannot be reproduced during simulation.
The complete design flow of synthesizing using Verilog code is given in Figure 1.

FPGA:
Field Programmable Gate Array (FPGA) is an integrated
circuit that consists of internal hardware blocks with user-programmable interconnects
to customize operation for a specific application. The interconnects can readily be
reprogrammed, allowing an FPGA to accommodate changes to a design or even support
a new application during the lifetime of the part.

FPGA Architecture

A basic FPGA architecture (Figure 2) consists of thousands of fundamental elements

called configurable logic blocks (CLBs) surrounded by a system of programmable
interconnects, called a fabric, that routes signals between CLBs. Input/output (I/O)
blocks interface between the FPGA and external devices.
Basic FPGA Architecture:

An Individual CLB:
 Depending on the manufacturer, the CLB may also be referred to as a logic block
(LB), a logic element (LE) or a logic cell (LC).

An individual CLB (Figure 3) is made up of several logic blocks. A lookup table

(LUT) is a characteristic feature of an FPGA. An LUT stores a predefined list of logic
outputs for any combination of inputs: LUTs with four to six input bits are widely used.
Standard logic functions such as multiplexers (mux), full adders (FAs) and flip-flops
are also common.

The number and arrangement of components in the CLB varies by device; the
simplified example in Figure 3 contains two three-input LUTs (1), an FA (3) and a D-
type flip-flop (5), plus a standard mux (2) and two muxes, (4) and (6), that are
configured during FPGA programming.

This simplified CLB has two modes of operation. In normal mode, the LUTs are
combined with Mux 2 to form a four-input LUT; in arithmetic mode, the LUT outputs
are fed as inputs to the FA together with a carry input from another CLB. Mux 4 selects
between the FA output or the LUT output. Mux 6 determines whether the operation is
asynchronous or synchronized to the FPGA clock via the D flip-flop.

Current-generation FPGAs include more complex CLBs capable of multiple

operations with a single block; CLBs can combine for more complex operations such as
multipliers, registers, counters and even digital signal processing (DSP) functions.

RESULT:
Thus, the VLSI Design flow and FPGA Architecture were studied.
CIRCUIT DIAGRAM:

MULTIPLEXER

DEMULTIPLEXER
EX.NO:2a DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF BASIC COMBINATIONAL CIRCUITS

AIM:
To design, simulate a basic combinational circuit (mux & demux) using Xilinx
software and implement using spartan 3E.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FPGA kit

THEORY:

Combinational circuits are fundamental building blocks in digital electronics.

They are designed to perform specific logical operations based solely on the current input,
without considering any previous inputs or the circuit's state. These circuits have no memory
or feedback, making their outputs depend only on the current input values.

Combinational circuits are used for various purposes, including data processing,
arithmetic operations, and logic functions. They are composed of interconnected logic gates,
such as AND, OR, NOT, XOR, NAND, and NOR gates. By combining these gates in
different ways, complex logic functions can be implemented to meet specific requirements in
digital systems.

Multiplexer and Demultiplexer are one such combinational circuits in digital

system design.

Multiplexer (MUX):
A multiplexer is a combinational circuit that selects one of the multiple input
data lines and directs it to a single output line. It operates based on a set of control signals
that determine which input is transmitted to the output. The number of control lines in a
multiplexer is determined by the formula 2^n, where 'n' is the number of input lines.
Demultiplexer (DEMUX):
A demultiplexer is a combinational circuit that takes a single input line and
distributes it to one of the multiple output lines. Similar to a multiplexer, a demultiplexer is
controlled by a set of control signals that specify the desired output line. The number of
control lines in a demultiplexer is also given by the formula 2^n, where 'n' is the number of
output lines.
TRUTH TABLE:

MULTIPLEXER

S0 S1 Y

0 0 I1

0 1 I2

1 0 I3

1 1 I4

DEMULTIPLEXER

I S0 S1 Y3 Y2 Y1 Y0

0 X X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0
PROGRAM:

//multiplexer
module mux(data_in, S, data_out);
input [3:0] data_in;
input [1:0] S;
output reg data_out;

always@(S or data_in)
begin
case(S)
2'b00: data_out=data_in[0];
2'b01: data_out=data_in[1];
2'b10: data_out=data_in[2];
2'b11: data_out=data_in[3];
endcase
end
endmodule

//demultiplexer
module demux(data_in, S, data_out);
input data_in;
input [1:0] S;
output reg [3:0] data_out;
always@(S or data_in)
begin
case(S)
2'b00: data_out=4'b0001;
2'b01: data_out=4'b0010;
2'b10: data_out=4'b0100;
2'b11: data_out=4'b1000;
endcase
end
endmodule

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.
OUTPUT:

MULTIPLEXER:

DEMULTIPLEXER:
 IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

IMPLEMENTATION:

Side switch connection with FPGA: LED connection with FPGA:

Switches FPGA LED FPGA

SW4 T14 L16 R1
SW5 T12 L15 R2
SW6 T9 L14 K3
SW7 T7 L13 T4
SW8 T2 L12 T5
SW9 G12 L11 R6
SW10 H1 L10 T8
SW11 R3 L9 R10

RESULT:
Thus, the basic combinational circuits were designed, simulated & implemented
using the Xilinx software and the output was verified.
SR FLIP-FLOP:

BLOCK DIAGRAM: TRURH TABLE:

clk reset S R Q

↑ 0 0 0 NC

↑ 0 0 1 0

↑ 0 1 0 1

↑ 0 1 1 X

↑ 1 X X 0

OUTPUT:
EX.NO:2b DESIGN, SIMULATION AND IMPLEMETATION OF
DATE: BASIC SEQUENTIAL CRICUITS (FLIP-FLOP)

AIM:
To design, simulate a flip-flop (basic sequential circuits) by using Xilinx software and
implement using spartan 3E.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FPGA kit

THEORY:
SEQUENTIAL CIRCUITS:
Sequential circuits are digital circuits that store and use the previous state information
to determine their next state. sequential circuits are different from combinational circuits in
that combinational circuits depend only on the present input to produce an output. Sequential
circuits, on the other hand, depend on both the present input and the previous state to
produce an output.

FLIP-FLOPS:
A flip-flop is a sequential logic circuit that has two stable states and can store one bit
of data. It is one of the basic building blocks of digital electronics.

SR FLIP-FLOP:
A SR flip-flop is a type of flip-flop that has two inputs: set (S) and reset (R). When the
S input is asserted, the flip-flop is set to the 1 state. When the R input is asserted, the flip-
flop is reset to the 0 state. If both the S and R inputs are asserted, the flip-flop enters an
invalid state.

JK FLIP-FLOP:
A JK flip-flop is a type of flip-flop that has two inputs: J and K. The J and K inputs are
used to control the setting and resetting of the flip-flop.

D FLIP-FLOP:
A D flip-flop (also known as a data flip-flop) is a type of flip-flop that has one input:
D. The D input is used to set the flip-flop to the desired state. When the clock signal is
asserted, the flip-flop changes state to the value of the D input.
JK FLIP-FLOP:

BLOCK DIAGRAM: TRUTH TABLE:

clk reset J K Q

↑ 0 0 0 Q

↑ 0 0 1 0

↑ 0 1 0 1

↑ 0 1 1 -Q

↑ 1 X X 0

OUTPUT:
T FLIP-FLOP:
A T flip-flop (also known as a toggle flip-flop) is a type of flip-flop that has one input:
T. The T input is used to toggle the flip-flop state. When the clock signal is asserted, the flip-
flop changes state to the opposite of its current state.

PROGRAM:

SR FLIP-FLOP:

module SRFlipFlop (clk,rst,s,r,q);

input wire clk,
input wire rst,
input wire s,
input wire r,
output reg q
always @(posedge clk or posedge rst) begin
if (rst)
q <= 1'b0;
else if (s && !r)
q <= 1'b1;
else if (!s && r)
q <= 1'b0;
end
endmodule

JK FLIP-FLOP:

module JKFlipFlop (clk,rst,j,k,q);

input wire clk,
input wire rst,
input wire j,
input wire k,
output reg q
always @(posedge clk or posedge rst) begin
if (rst)
q <= 1'b0;
else if (j && !k)
q <= 1'b1;
else if (!j && k)
q <= 1'b0;
else if (j && k)
q <= ~q;
end
endmodule
D FLIP-FLOP:

BLOCK DIAGRAM: TRUTH TABLE:

clk reset D Q

↑ 0 0 0

↑ 0 1 1

↑ 1 X 0

OUTPUT:
D FLIP-FLOP:

module DFlipFlop (clk,rst,d,q);

input wire clk,
input wire rst,
input wire d,
output reg q
always @(posedge clk or posedge rst) begin
if (rst)
q <= 1'b0;
else
q <= d;
end
endmodule

T FLIP-FLOP:

module TFlipFlop (clk,rst,t,q);

input wire clk,
input wire rst,
input wire t,
output reg q,
always @(posedge clk or posedge rst) begin
if (rst)
q <= 1'b0;
else if (t)
q <= ~q;
end
endmodule

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.
T FLIP-FLOP:

BLOCK DIAGRAM: TRUTH TABLE:

clk reset T Q
↑ 0 0 0
↑ 0 1 1
↑ 0 0 1
↑ 0 1 0
↑ 1 X 0

OUTPUT:
 IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

IMPLEMENTATION:

Side switch connection with FPGA: LED connection with FPGA:

Switches FPGA LED FPGA

SW4 T14 L16 R1
SW5 T12 L15 R2
SW6 T9 L14 K3
SW7 T7 L13 T4
SW8 T2 L12 T5
SW9 G12 L11 R6
SW10 H1 L10 T8
SW11 R3 L9 R10

RESULT:
Thus, the flip-flops (basic sequential circuits) were designed, simulated and
implemented by using Xilinx software and output was verified.
8- BIT ADDER:

BLOCK DIAGRAM:

TRUTH TABLE:
EX.NO:3a DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF ADDER

AIM:
To design, simulate and implement 8 bit adder using Xilinx software.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FGPA kit

THEORY:
8-bit addition (Ripple Carry adder):
The n bit adder built from a number of one-bit full address is known as ripple
carry adder because of the carry is completed. The addition is not complete until n-1 th adder
has computed its n-1 output those results depends upon a input n and so on down the line, so
the critical delay path from the 0 bit.

PROGRAM:
8-bit adder:
Data flowing modelling:

module adder (a, b, s, c);

input [7:0] a, b;
output [7:0] s;
output c;
assign {c, s} = a + b;
end module
INPUT:

OUTPUT:
PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.
Side switch connection with FPGA:

Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
RESULT:
Thus the 8-bit adder was designed, simulated and implemented by using Xilinx
software and output was verified.
BLOCK DIAGRAM:
EX.NO:3b DESIGN, SIMULATION AND
DATE: IMPLEMENTATION OF MULTIPLIER

AIM:
To design, simulate and implement 8-bit multiplier circuit using Xilinx software.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FGPA kit

THEORY:

Multiplication of two elements in the polynomial basis can be accomplished in

the normal way of multiplication, but there are a number of ways to speed up multiplication,
especially in hardware. In this type the multiplication can done parallel counter and it is
generate carry. The multiplication is independent of the carry so we can perform N number
of multiplication independent of carry.
Binary Multiplication can be accomplished by several approaches. The approach
presented here is realised entirely with combinational circuits. Such a circuit is called an
array multiplier. The term array is used to describe the multiplier because the multiplier is
organized as an array structure. Each row, called a partial product is formed by a bit-by-bit
multiplication of each operand.
For example, a partial product is formed, when each bit of operand 'a' is
multiplied by b0 resulting in a a3b0, a2b0, a1b0, a0b0. The binary multiplication table is
identical to the AND truth table.
Each product bit is formed by adding partial product column. The product
equations, including the carry-in {c(x)} from column (x-1) are (the plus sign indicates
addition not OR). Each product term, p(x) is formed by AND gates and collection of produce
terms needed for the multiplier. By adding appropriate P term outputs, the multiplier output
equations are realised as shown in figure.
ARRAY MULTIPLIER:

TRUTH TABLE:

INPUT OUTPUT

A B S

00101100 11011001 0000000011000100

10101010 01010101 0000000001111110

11110000 00001111 0000000011110000

01010101 10101010 0000000001100110

11001100 00110011 0000000011001100

10000000 10000000 0000000000000000

01111111 10000000 0111111100000000

00111100 00111100 0000000010000100

PROGRAM:

8-bit multiplier:

module multi(a,b,c);
input [7:0] a,b;
output [15:0]c;
assign c=a*b;
end module

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10.File→ save constraints
11.Then go to the Xilinx window →Implement design
12.Click generate program file→ run.
13.Switch ON the kit.
14.Download the program to the kit by clicking on impact option (tools)
15.Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16.Open the bit file→ yes
17.Right Click on chip (image) and collect program, “success message appears”.
INPUT:

OUTPUT:
Side switch connection with FPGA:

Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10

RESULT:
Thus the 8-bit multiplier was designed, simulated and implemented successfully using
Xilinx software and the output was verified.
UNIVERSAL SHIFT REGISTER:

TABLE:

S1 S0 Register Operation

Locked State
0 0
(No Change)

0 1 Shift Right

1 0 Shift Left

1 1 Parallel Load
EX.NO:4 DESIGN, SIMULATION AND IMPLEMENTATION OF
DATE: UNIVERSAL SHIFT REGISTER

AIM:
To design, simulate and implement universal shift register using Xilinx software.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FGPA kit

THEORY:
A Unidirectional shift register is a register that can capable of transferring data
in only one direction. Whereas the register that is capable of transferring data in both left and
right direction is called a ‘bidirectional shift register’. Now let we have a register which can
capable to transfer data in both the shift-right and shift-left, along with the necessary input
and output terminals for parallel transfer, then it is called a shift register with parallel load or
‘universal shift register’.
A shift-right control to enable the shift-right operation and the serial input and
output lines associated with the shift-right. A shift-left control to enable the shift-left
operation and the serial input and output lines associated with the shift-left.
A parallel-load control to enable a parallel transfer and the n-input lines
associated with the parallel transfer. n-parallel output lines. A clear control to clear the
register to 0. A CLK input for clock pulses to synchronize all operations. A control state that
leaves the information in the register unchanged even though clock pulses are continuously
applied.
The applications of a universal shift register include the following.
• Used in micro-controllers for I/O expansion
• Used as a memory element in digital electronics like computers.
• Used in time delay applications
• Used as frequency counters, binary counters, and Digital clocks
• Used in data manipulation applications.
OUTPUT:
No Change S - 00

Shift Right S - 01
PROGRAM:

module shift (a, s, clk, p);

input [3:0] a;
input [3:0] s;
input clk;
output reg [3:0] p;
initial p<=a;
always@ (posedge clk)
begin
case(s)
2'b00:
begin
p[3]<=a[3]; p[2]<=a[2];
p[1]<=a[1]; p[0]<=a[1];
$display(" no change ");
end
2'b01:
begin
p[3]<=a[0]; p[2]<=a[3];
p[1]<=a[2]; p[0]<=a[1];
$display(" shift right");
end
2'b10:
begin
p[0]<=a[3]; p[1]<=a[0];
p[2]<=a[1]; p[3]<=a[2];
$display(" shift left");
end
2'b11:
begin
p[0]<=a[0]; p[1]<=a[1];
p[2]<=a[2]; p[3]<=a[3];
$display(" parallel load");
end
endcase
end
end module
Shift Left S-10

Parallel load S-11

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and
types LED under site columns.
10.File→ save constraints
11.Then go to the Xilinx window →Implement design
12.Click generate program file→ run.
13.Switch ON the kit.
14.Download the program to the kit by clicking on impact option (tools)
15.Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16.Open the bit file→ yes
17.Right Click on chip (image) and collect program, “success message appears”.
Side switch connection with FPGA:
Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
RESULT:
Thus the universal shift register was designed, simulated and implemented
successfully using Xilinx software and the output was verified.
BLOCK DIAGRAM:

PIN DISCRIPTION:

S.NO. Name of the pin Direction Width Description

1. address Input 4 Input address
2. ip Input 4 Input data to memory
3. rd_wr Input 1 Control signal
1 = Read from memory
2 = Write in to memory
4. clk Input 1 Clock input
5. op Output 4 Output read from memory
EX.NO:5 DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF MEMORIES

AIM:
To design, simulate and implement memories using Xilinx software.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FGPA kit

THEORY:
Static RAM is a type of RAM that holds data without external refresh for as long as
power supplied to the circuit SRAM memory cell is a bit-state flip-flop maybe in either of
two circuitry to be 1 or 0. An SRAM cell has three different states stand by(the circuit is
idle) reading(the data has been requested) or writing(updating the content)
To read a data from memory cell, the following steps must be occurring.
i. Before the clock, transition (low to high) occur that initialise the read operation
the row and column must be applied to the adder input pins.
ii. The chip must be selected.
iii. And the write enable must be high single part RAM with asynchronous read.
The following descriptions are directly mappable onto distributing RAM only.

PROGRAM:
module memory(op,ip,rd_wr,clk,address);
output reg [3:0] op;
input [3:0] ip;
input [3:0] address;
input rd_wr,clk;
reg [3:0] memory[15:0];
OUTPUT:

IMPLEMENTATION:
Side switch connection with FPGA: LED connection with FPGA:

Switches FPGA LED FPGA

SW4 T14
L16 R1
SW5 T12
SW6 T9 L15 R2
SW7 T7 L14 K3
SW8 T2 L13 T4
SW9 G12
L12 T5
SW10 H1
SW11 R3 L11 R6
SW12 N11 L10 T8
SW13 N3
L9 R10
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11
 always @ (posedge clk) begin
if (rd_wr) begin
memory[address] <= ip;
end else begin
op <= memory[address];
end
end
endmodule

PROCEDURE:

SIMULATION:
1.Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

RESULT:
Thus, the memories were designed, simulated and implemented successfully using
Xilinx Software and output was verified.
EX NO:6 DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF FINITE STATE MACHINE

AIM:
To design, simulate and implement the finite state machine using Xilinx software.
APPARATUS REQUIRED:
 PC with windows
 ISE Design Suite14.3
 Spartan 3E FPGA bit

THEORY:

MEALY MODEL:
Analysis describes what a given circuit will do under certain operating conditions.
The behaviour of a clocked sequential circuit is determined from the inputs, the outputs, and
the state of its flip-flops. The outputs and the next state are both a function of the inputs and
the present state. The analysis of a sequential circuit consists of obtaining a table or a
diagram for the time sequence of inputs, outputs, and internal states. It is also possible to
write Boolean expressions that describe the behavior of the sequential circuit. These
expressions must include the necessary time sequence, either directly or indirectly. A logic
diagram is recognized as a clocked sequential circuit if it includes flip-flops with clock
inputs. The flip-flops may be of any type, and the logic diagram may or may not include
combinational logic gates.
State Equations: The behavior of a clocked sequential circuit can be described
algebraically by means of state equations. A state equation (also called a transition equation)
specifies the next state as a function of the present state and inputs. Consider the sequential
circuit. It acts as a 0-detector by asserting its output when a 0 is detected in a stream of 1s.
A(t + 1) = A(t)x(t) + B(t)x(t) ; B(t + 1) = A’(t)x(t); y(t) = [A(t) + B(t)]x’(t)
A state equation is an algebraic expression that specifies the condition for a flip-
flop state transition. The left side of the equation, with (t + 1), denotes the next state of the
flip-flop one clock edge later. The right side of the equation is a Boolean expression that
specifies the present state and input conditions that make the next state equal to 1. Since all
the variables in the Boolean expressions are a function of the present state, we can omit the
designation ( t ) after each variable for convenience and can express the state equations in the
more compact form
A(t + 1) =Ax + Bx ; B(t + 1) =A’x ; y = Ax’+ Bx’
STATE DIAGRAM:

MEALY MODEL:

MOORE MODEL:
MOORE MODEL:
A Moore machine is defined as a sequential network whose output is a function
of the present state only. Moore state machine output remains same as long as state
machine remains in that state. In Moore machine, every combination must be represented
with a different internal state. Moore machine is faster because the outputs are calculated
during the previous clock cycle. Thus, the outputs are ready, very close to the current
clock cycle.

PROGRAM:
module MooreAndMealyFSM(clk, reset, in, moore_out, mealy_out );
input clk;
input reset;
input in;
output reg moore_out;
output mealy_out;

parameter STATE_A = 1'b0;

parameter STATE_B = 1'b1;
reg state_reg;

always @(posedge clk, posedge reset)

begin
if (reset)
begin
state_reg <= STATE_A; // Reset state to STATE_A
end
else
begin
case(state_reg)
STATE_A:
begin
if (in)
STATE TABLE:

CURRENT NEXT MOORE MEALY

INPUT RESET
STATE STATE OUTPUT OUTPUT

A 1 0 B 0 1

A 0 0 A 0 0

B 1 0 B 1 0

B 0 0 A 1 0

X X 1 A 0 0
 begin
state_reg <= STATE_B; // Transition to STATE_B if input is high
end
end
STATE_B:
begin
if (!in)
begin
state_reg <= STATE_A; // Transition to STATE_A if input is low
end
end
endcase
end
end

// Moore output
always @(posedge clk, posedge reset)
begin
if (reset)
begin
moore_out <= 1'b0; // Reset Moore output to 0
end
else
begin
case(state_reg)
STATE_A: moore_out <= 1'b0;
STATE_B: moore_out <= 1'b1;
endcase
end
end
OUTPUT:
// Mealy output
always @(posedge clk, posedge reset)
begin
if (reset)
begin
mealy_out <= 1'b0; // Reset Mealy output to 0
end
else
begin
if (state_reg == STATE_A && in)
begin
mealy_out <= 1'b1;
end
else
begin
mealy_out <= 1'b0;
end
end
end
endmodule

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.
IMPLEMENTATION:
Side switch connection with FPGA:
Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
 IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

RESULT:
Thus, the finite state machine was designed, simulated and implemented
successfully using Xilinx software and output was verified successfully.
TRUTH TABLE:

Clk Reset Up_down Count

1 0 0 Count - 1

1 0 1 Count + 1

1 1 X 0

OUTPUT:
EX.NO:7 DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design, simulate and implement 3-bit synchronous up/down counter using
Xilinx software

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FGPA kit

THEORY:
COUNTER:
A counter is a digital circuit that tracks and displays the number of events or
occurrences. It increments by one with each input pulse, counting up from an initial value.
Counters are commonly used in electronics and digital systems for tasks like tallying, timing,
and control purposes.

SYNCHRONOUS UP/DOWN COUNTER:

A synchronous up/down counter is a digital circuit used in electronics and digital logic
design to count either up (increment) or down (decrement) based on external control signals.

PROGRAM:
module UpDownCounter3 (clk,reset,up_down,count);
input clk,reset,up_down;
output reg [2:0] count;
initial begin
count = 3’b000;
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
count <= 3'b000;
end
else
IMPLEMENTATION:
Side switch connection with FPGA:
Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
 begin
if (up_down) begin
count <= count + 1;
end
else begin
count <= count - 1;
end
end
end
endmodule

PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

RESULT:
Thus, the 3-bit synchronous up/down counter was designed, simulated and
implemented using Xilinx software and output was verified.
TRUTH TABLE:

Clk Reset Up Down Count

1 0 1 0 Count - 1

1 0 0 1 Count + 1

1 1 X X 0

1 0 1 1 No change

1 0 0 0 No change

OUTPUT:
EX.NO:8 DESIGN, SIMULATION AND IMPLEMENTATION
DATE: OF ASYNCHRONOUS UP/DOWN COUNTER

AIM:
To design, simulate and implement 4-bit asynchronous up/down counter using Xilinx
software.

APPARATUS REQUIRED:
 PC with windows
 Xilinx 14.3
 Spartan 3E FPGA kit

THEORY:
ASYNCHRONOUS UP/DOWN COUNTER:
An asynchronous up/down counter, also known as a ripple counter, is a type of digital
counter circuit that can count up or down based on external control signals without the use of
a common clock signal.

Asynchronous Operation: Unlike synchronous counters, asynchronous counters do not

have a common clock signal. Instead, each flip-flop triggers the next one in sequence. When
counting up, the first flip-flop responds to the 'up' signal, and this, in turn, triggers the next
flip-flop, and so on.

PROGRAM:
module async_4bit_up_down_counter (clk,rst,up,down,count);
input clk, rst, up, down;
output reg [3:0] count;
initial begin
count = 4’b0000;
end
always @(posedge clk or posedge rst)
begin
if (rst)
count <= 4'b0000;
else if (up)
count <= count + 1;
else if (down)
count <= count - 1;
end
endmodule
IMPLEMENTATION:
Side switch connection with FPGA:
Switches FPGA
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11

LED connection with FPGA:

LED FPGA
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
PROCEDURE:

SIMULATION:
1. Open ISE design suite.
2. Click New project→ Type the file name→ Select the location→ Next
3. Choose the reg specification in the dialog box
4. Now click on project →New Source → choose Verilog module → specific file.
5. Type the program and save
6. Select any synthesis → Check syntax
7. Load the program into test bench waveform and give input and finally get the
output in the form of waveform.

IMPLEMENTATION:
8. From the user constraint, select I/O port synthesis, click yes→ close
9. Select I/O pin assign, configure I/P, 2 port pin to corresponding switches and types
LED under site columns.
10. File→ save constraints
11. Then go to the Xilinx window →Implement design
12. Click generate program file→ run.
13. Switch ON the kit.
14. Download the program to the kit by clicking on impact option (tools)
15. Now a window appears, click on boundary scan. Right click ON the chip image
and select assign new configuration.
16. Open the bit file→ yes
17. Right Click on chip (image) and collect program, “success message appears”.

RESULT:
Thus, the 4-bit asynchronous up/down counter was designed, simulated and
implemented using Xilinx software and output was verified.\
TRUTH TABLE:

CMOS – NAND CMOS-NOR

A B Y A B Y

0 0 1 0 0 1

0 1 1 0 1 0

1 0 1 1 0 0

1 1 0 1 1 0

LAYOUT:

CMOS-NAND:
EX.NO:9a DESIGN AND SIMULATION OF CMOS BASIC GATES
DATE: (Automatic & Manual Layout)

AIM:
To design and simulate CMOS – basic gates & generate its layout manually and
automatically using Microwind and DSCH software.

APPARATUS REQUIRED:
 PC with windows
 Microwind 3.1
 DSCH 3.0.1

THEORY:

BASIC CMOS GATES:

CMOS NAND and NOR Gates:

CMOS NAND and NOR gates are the cornerstone of digital logic circuits.
These gates are designed using pairs of complementary metal-oxide-semiconductor (CMOS)
transistors, comprising both P-channel (PMOS) and N-channel (NMOS) transistors.

 In a CMOS NAND gate, when both inputs are low (0), the NMOS transistors conduct,
establishing a low resistance path to ground, resulting in a high (1) output.
 Conversely, in a CMOS NOR gate, when both inputs are high (1), the PMOS
transistors conduct, creating a low resistance path to the power supply, yielding a low
(0) output.

CMOS technology offers low power consumption, excellent noise immunity, and
is extensively used in digital integrated circuits.
CMOS NOR:

AUTOMATIC GENERATION (DSCH SOFTWARE):

CIRCUIT DIAGRAM:

CMOS NAND:
PROCEDURE:

MANUAL GENERATION:
1. Open the Microwind 3.1 software.
2. Click file → name.
3. View → Pallet of layers.
4. Draw the stick diagram using pallet window.
5. Add Vss and Vdd connection.
6. Give the input and are visible node for output.
7. To verify the functionality → simulate → run simulator → voltage V o time
(default).
8. Finally get the output in the form of waveform.
AUTOMATIC GENERATION:
DSCH SOFTWARE:
1. Open the DSCH 3.0.1 software.
2. Click → File → New.
3. Click → View → Symbol library.
4. Draw the circuit diagram using Symbol library window.
5. Add Button, clock, supply and light.
6. To verify the functionality → simulate → start simulation.
7. Click → Timing Diagram get the output in the form of waveform.
8. Click → File → Save as → Create New folder → Give name for file → save.
9. Click → File → Make Verilog File.

MICROWIND SOFTWARE:
1. Open the Microwind 3.1 software.
2. Click → Compile → Compile Verilog File.
3. Select → you saved file with .v extension.
4. Click → Compile →Back to editor.
5. Remove any unwanted connection in this stick diagram.
6. To verify the functionality → simulate → run simulation → voltage Vo time
(default).
7. Finally get the output in the form of waveform.
CMOS NOR:

OUTPUT (MICROWIND):

CMOS NAND:
CMOS NOR
RESULT:
Thus, the CMOS – basic gates were designed, simulated & its layout was
generated manually and automatically using Microwind and DSCH software and output was
verified.
 D FLIP FLOP SR FLIP FLOP

Clock D Q Q’ Description INPUTS OUTPUT STATE

CLK S R Q
↑ X Q Q’ Memory no ↑ 0 0 No change Previous
change
↑ 0 1 0 Reset
↑ 0 0 1 Reset
↑ 1 0 1 Set
↑ 1 1 0 Set
↑ 1 1 X Forbidden

LAYOUT:

D FLIP FLOP:
EX.NO:9b DESIGN AND SIMULATION OF FLIPFLOPS
DATE: (Automatic & Manual Layout)

AIM:
To design and simulate flipflops & generate its layout manually and
automatically using Microwind and DSCH software.

APPARATUS REQUIRED:
 PC with windows
 Microwind 3.1
 DSCH 3.0.1

THEORY:
FLIP FLOPS:

D Flip-Flop:
The D flip-flop, often called the Data or Delay flip-flop, is a vital component
in sequential logic. It is used for storing a single bit of data. The D flip-flop operates by
transferring the input data (D) to the output (Q) when triggered by a clock signal. The type of
edge that triggers the transfer (positive or negative) depends on the specific D flip-flop
design. This feature is valuable in synchronizing data in sequential systems, ensuring that
changes in the input are captured and reflected in the output at specific moments.

SR Flip-Flop:
The SR flip-flop, or Set-Reset flip-flop, is a bistable multivibrator with two
inputs: S (Set) and R (Reset). When S is set to 1, the Q output is forced to 1, and when R is
set to 1, the Q output is driven to 0. It's crucial to use SR flip-flops cautiously, as
simultaneous assertion of both S and R can lead to an indeterminate state.

SR flip-flops are employed in scenarios where you need to set or reset a stored
state, often in control or memory applications.
SR FLIP FLOP

‘
AUTOMATIC GENERATION (DSCH SOFTWARE):

CIRCUIT DIAGRAM:

D FLIP FLOP
PROCEDURE:

MANUAL GENERATION:
1. Open the Microwind 3.1 software.
2. Click file → name.
3. View → Pallet of layers.
4. Draw the stick diagram using pallet window.
5. Add Vss and Vdd connection.
6. Give the input and are visible node for output.
7. To verify the functionality → simulate → run simulator → voltage Vo time
(default).
8. Finally get the output in the form of waveform.
AUTOMATIC GENERATION:
DSCH SOFTWARE:
1. Open the DSCH 3.0.1 software.
2. Click → File → New.
3. Click → View → Symbol library.
4. Draw the circuit diagram using Symbol library window.
5. Add Button, clock, supply and light.
6. To verify the functionality → simulate → start simulation.
7. Click → Timing Diagram get the output in the form of waveform.
8. Click → File → Save as → Create New folder → Give name for file → save.
9. Click → File → Make Verilog File.

MICROWIND SOFTWARE:
1. Open the Microwind 3.1 software.
2. Click → Compile → Compile Verilog File.
3. Select → you saved file with .v extension.
4. Click → Compile →Back to editor.
5. Remove any unwanted connection in this stick diagram.
6. To verify the functionality → simulate → run simulation → voltage Vo time
(default).
7. Finally get the output in the form of waveform.
SR FLIP FLOP

OUTPUT (MICROWIND):

D FLIP FLOP
SR FLIP FLOP
RESULT:
Thus, the flipflops were designed, simulated & its layout was generated
manually and automatically using Microwind and DSCH software and output was verified.
TRUTH TABLE:

4-BIT UP COUNTER:

Clk Out1 Out2 Out3 Out4

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

4-BIT DOWN COUNTER:

Clk Out1 Out2 Out3 Out4

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
EX.NO:10 DESIGN AND SIMULATION OF
DATE: SYNCHRONOUS COUNTER USING FLIPFLOPS
(Automatic & Manual Layout)

AIM:
To design and simulate 4-bit synchronous up/down counter using flipflops &
generate its layout manually and automatically using Microwind and DSCH software.

APPARATUS REQUIRED:
 PC with windows
 Microwind 3.1
 DSCH 3.0.1

THEORY:
COUNTER:
A counter is a digital circuit that tracks and displays the number of events or
occurrences. It increments by one with each input pulse, counting up from an initial value.
Counters are commonly used in electronics and digital systems for tasks like tallying, timing,
and control purposes.

A 4-bit synchronous up counter is a digital circuit that counts in binary from 0 to 15

(2^4 - 1).

1. 4-bit: This indicates that the counter has four flip-flops, and each flip-flop represents one
bit. The counter can represent values from 0 to 15 in binary (0000 to 1111).

2. Synchronous: Synchronous means that all flip-flops in the counter change their states
simultaneously, triggered by a common clock signal. This is in contrast to asynchronous
counters where the flip-flops change based on individual clock signals.
LAYOUT:

4-BIT UP COUNTER:

4-BIT DOWN COUNTER:

PROCEDURE:

MANUAL GENERATION:
1. Open the Microwind 3.1 software.
2. Click file → name.
3. View → Pallet of layers.
4. Draw the stick diagram using pallet window.
5. Add Vss and Vdd connection.
6. Give the input and are visible node for output.
7. To verify the functionality → simulate → run simulator → voltage Vo time
(default).
8. Finally get the output in the form of waveform.
AUTOMATIC GENERATION:
DSCH SOFTWARE:
1. Open the DSCH 3.0.1 software.
2. Click → File → New.
3. Click → View → Symbol library.
4. Draw the circuit diagram using Symbol library window.
5. Add Button, clock, supply and light.
6. To verify the functionality → simulate → start simulation.
7. Click → Timing Diagram get the output in the form of waveform.
8. Click → File → Save as → Create New folder → Give name for file → save.
9. Click → File → Make Verilog File.

MICROWIND SOFTWARE:
1. Open the Microwind 3.1 software.
2. Click → Compile → Compile Verilog File.
3. Select → you saved file with .v extension.
4. Click → Compile →Back to editor.
5. Remove any unwanted connection in this stick diagram.
6. To verify the functionality → simulate → run simulation → voltage Vo time
(default).
7. Finally get the output in the form of waveform.
AUTOMATIC GENERATION (DSCH SOFTWARE):

CIRCUIT DIAGRAM

4-BIT UP COUNTER:

4-BIT DOWN COUNTER:

OUTPUT (MICROWIND):

4-BIT UP COUNTER:

4-BIT DOWN COUNTER:

RESULT:
Thus, a 4-bit synchronous up/down counter using flipflops was simulated &
its layout was generated manually and automatically using Microwind and DSCH software
and output was verified.
EX.NO:11 STUDY OF TANNER TOOL
DATE:

AIM:
To study the basic circuit designing and simulation procedure using tanner tool.
PROCEDURE FOR TANNER TOOL:
1. Open S-edit window  Click file  New design  Type the design name  Choose
the desired folder  Ok.
2. Select your design window in left side window. Add browse.
3. Select Add  My documents  tanner EDA  tanner tools VLSI  process  generic
250 nm device  Open.
4. Repeat the step 3 up to process  Standard Library Standard I/O devices  add
MISC, spice elements, spice commands) by repeating step 4.
5. Cell  New view  view type  Schematic ok.
6. Select the elements which you need by clicking instance and then place it.
7. For moving the element  Click the element and place it.
8. For flipping  Shift + N.
9. For rotating  Shift + R.
10.Use input ports  and output ports  and other using icons.
11.To setup simulation  setup  spice simulator, select AC analysis  give start
12.frequency, step frequency = 10 MHz, No. of frequency = 25, Sweep time in dB Go to
general  Library files  browse  documents  tanner EDA  tanner tools 
process  generic  250nm.
13.Run this simulation by clicking icon.
14.Verify waveform at TCN window and values of the TLE window.

RESULT:
Thus, the basic circuit designing and simulation procedure using tanner tool
was studied.
CIRCUIT DIAGRAM:

INVERTING AMPLIFIER
EX.NO:12 DESIGN AND SIMULATION OF
DATE: CMOS INVERTING AMPLIFIER

AIM:
To design and simulate a CMOS inverting amplifier using Tanner Tool.

SOFTWARE REQUIRED:
 Tanner Software

THEORY:

CMOS inverting amplifier:

The CMOS inverter can be used as an amplifier properly biased in the transistor
region of its voltage transistor characteristics (VTL).
The various configuration:
1)Achieve load inverter
2)Current source load inverter
3)Push Pull inverter

Voltage gain=(-gM1+gM2)(r01||r02)
Output Resistance=r01||r02
Bandwidth=((1/r01)+(1/r02))/(CBD1+CGD1+CBD2+CGD2)
OUTPUT:
PROCEDURE:

1. Repeat up to 7steps in general procedure.

2. Generic 250nm contains PMOS and NMOS (25V).
3. Spice elements contains voltage source (DC, AC).
4. MISC contains VDD and ground.
5. Spice commands contains print voltage AC measure gain, gain bandwidth
product.
6. Repeat the steps from 8 to 14 from the general procedure to complete the
schematic design.
7. Obtain the spice code using T-edit
8. Obtain the output waveform using W-edit

RESULT:
Thus, the CMOS inverting amplifier circuit was designed and simulated by
using Tanner EDA and the output was verified successfully.
CIRCUIT DIAGRAM:

COMMON SOURCE

COMMON DRAIN
EX NO:13 DESIGN AND SIMULATION OF BASIC CMOS
DATE: AMPLIFIERS (CS, CD & CG CONFIGURATIONS)

AIM:
To design and simulate basic CMOS amplifier circuits (common source, common
drain, common gate) using tanner software.

SOFTWARE REQUIRED:
Tanner EDA

THEORY:
Common Drain Amplifier (Source Follower):
The common drain amplifier figure shows the source follower circuit in which drain
terminal of the device is common. In this circuit the drain terminal is directly connected to
VDD. In CS amplifier analysis we have seen that in order to achieve the high voltage gain
the load impedance should be as high as possible. Therefore, for low impedance load the
buffer must be placed after the amplifier to drive the load with negligible loss of the signal
level. The source follower thus worked as a buffer stage. The source follower is also called
as the common drain amplifier. In this circuit, the signal at the gate is sensed and drives the
load at the source which allows the source potential to follow the gate voltage. The drawback
of source follower is nonlinearity due to body effect and poor driving capability of the input
signal.
Common Source Amplifier:
In this circuit the MOSFET converts variations in the gate-source voltage into a small
signal drain current which passes through a resistive load and generates the amplified voltage
across the load resistor. the voltage gain of CS amplifier is depends upon the
transconductance gm, the linear resistor Ro and load. In order to increase the gain, we have to
increase the Gm. In turn we have to increase the ratio.
Common Gate amplifier:
In common source amplifier and source follower circuits, the input signal are applied
to the gate of a MOSFET. It is also possible to apply the input signal to the source terminal
by keeping common gate terminal. This type of amplifier is called as common gate amplifier.
The CG amplifier in which the input signal is sensed at the source terminal and the output is
produced at the drain terminal. The gate terminal is connected to Vb i.e., dc potential which
will maintain the proper operating conditions.
CIRCUIT DIAGRAM

COMMON GATE

OUTPUT:
COMMON SOURCE:
PROCEDURE:
1. Repeat up to 7steps in general procedure.
2. Generic 250nm contains PMOS and NMOS (25V).
3. Spice elements contains voltage source (DC, AC).
4. MISC contains VDD and ground.
5. Spice commands contains print voltage AC measure gain, gain bandwidth
product.
6. Repeat the steps from 8 to 14 from the general procedure to complete the
schematic design.
7. Obtain the spice code using T-edit
8. Obtain the output waveform using W-edit
OUTPUT:
COMMON DRAIN

COMMON GATE
RESULT:
Thus, the basic CMOS amplifier circuits (CG,CS,CD) were designed and
simulated using Tanner EDA and the output was verified successfully.
CIRCUIT DIAGRAM:

DIFFERENTIAL AMPLIFIER
EX NO:14 DESIGN AND SIMULATION OF FIVE TRANSISTOR
DATE: DIFFERENTIAL AMPLIFIER

AIM:
To design and simulate five transistor differential amplifier circuit using tanner
software.

SOFTWARE REQUIRED:
Tanner software

THEORY:

DIFFERENTIAL AMPLIFIER:
Differential Amplifier is a device that is used to amplify the difference in voltage of
the two input signals. Differential amplifier is an important building block in integrated
circuits of analog system.
Vo = Ad (V1-V2)

Here, a voltage different present at the inverting and non-inverting terminal gets
amplified and thus an amplifier output is received. The differential amplifier can be
constructed by making use of BJT and FET’s.
OUTPUT:
COMMON MODE
KEY TERMS:
Voltage gain:
Common mode gain, Ac = Vo / Vc
CMRR (common mode rejection ratio):
CMRR stands for Common Mode Rejection Ratio, it is given as the ratio of
differential mode gain to the common mode gain.
CMRR = Ad / Ac
In dB, CMRR =20log10 Ad
ADVANTAGES OF DIFFERENTIAL AMPLIFIER:
1. Noise Immunity
2. Drift Immunity

PROCEDURE:
1. Repeat up to 7steps in general procedure.
2. Generic 250nm contains PMOS and NMOS (25V).
3. Spice elements contains voltage source (DC, AC).
4. MISC contains VDD and ground.
5. Spice commands contains print voltage AC measure gain, gain bandwidth product.
6. Repeat the steps from 8 to 14 from the general procedure to complete the schematic
design.
7. Obtain the spice code using T-edit
8. Obtain the output waveform using W-edit
OUTPUT:
DIFFERENTIAL MODE
RESULT:
Thus, five transistor differential amplifier circuit was designed and simulated
using Tanner EDA and the output was verified successfully.