Electronic design automation

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD),[1]
is a category of software tools for designing electronic systems such as integrated circuits and printed circuit
boards. The tools work together in a design flow that chip designers use to design and analyze entire
semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are
essential for their design; this article in particular describes EDA specifically with respect to integrated
circuits (ICs).

History

Early days

The earliest electronic design automation is attributed to IBM with the documentation of its 700 series
computers in the 1950s.[2]

Prior to the development of EDA, integrated circuits were designed by hand and manually laid out.[3]
Some advanced shops used geometric software to generate tapes for a Gerber photoplotter, responsible for
generating a monochromatic exposure image, but even those copied digital recordings of mechanically
drawn components. The process was fundamentally graphic, with the translation from electronics to
graphics done manually; the best-known company from this era was Calma, whose GDSII format is still in
use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the
first placement and routing tools were developed; as this occurred, the proceedings of the Design
Automation Conference catalogued the large majority of the developments of the time.[3]

The next era began following the publication of "Introduction to VLSI Systems" by Carver Mead and
Lynn Conway in 1980; considered the standard textbook for chip design.[4] The result was an increase in
the complexity of the chips that could be designed, with improved access to design verification tools that
used logic simulation. The chips were easier to lay out and more likely to function correctly, since their
designs could be simulated more thoroughly prior to construction. Although the languages and tools have
evolved, this general approach of specifying the desired behavior in a textual programming language and
letting the tools derive the detailed physical design remains the basis of digital IC design today.

The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI
Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used are the
Espresso heuristic logic minimizer, responsible for circuit complexity reductions and Magic, a computer-
aided design platform. Another crucial development was the formation of MOSIS, a consortium of
universities and fabricators that developed an inexpensive way to train student chip designers by producing
real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC
processes and pack a large number of projects per wafer, with several copies of chips from each project
remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost, as
they saw the program as helpful to their own long-term growth.

Birth of commercial EDA

1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such
as Hewlett-Packard, Tektronix and Intel, had pursued EDA internally, with managers and developers
beginning to spin out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor
Graphics and Valid Logic Systems were all founded around this time and collectively referred to as DMV.
In 1981, the U.S. Department of Defense additionally began funding of VHDL as a hardware description
language. Within a few years, there were many companies specializing in EDA, each with a slightly
different emphasis.

The first trade show for EDA was held at the Design Automation Conference in 1984 and in 1986, Verilog,
another popular high-level design language, was first introduced as a hardware description language by
Gateway Design Automation. Simulators quickly followed these introductions, permitting direct simulation
of chip designs and executable specifications. Within several years, back-ends were developed to perform
logic synthesis.

Modern day

Current digital flows are extremely modular, with front ends producing standardized design descriptions
that compile into invocations of units similar to cells without regard to their individual technology. Cells
implement logic or other electronic functions via the utilisation of a particular integrated circuit technology.
Fabricators generally provide libraries of components for their production processes, with simulation
models that fit standard simulation tools.

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to
analog design (such as matching concepts).[5] Hence, analog EDA tools are far less modular, since many
more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor
technology.[6] Some users are foundry operators, who operate the semiconductor fabrication facilities
("fabs") and additional individuals responsible for utilising the technology design-service companies who
use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for
programming design functionality into FPGAs or field-programmable gate arrays, customisable integrated
circuit designs.

Software focuses

Design

Design flow primarily remains characterised via several primary components; these include:

High-level synthesis (additionally known as behavioral synthesis or algorithmic synthesis) –

The high-level design description (e.g. in C/C++) is converted into RTL or the register
transfer level, responsible for representing circuitry via the utilisation of interactions between
registers.
 Logic synthesis – The translation of RTL design description (e.g. written in Verilog or VHDL)
into a discrete netlist or representation of logic gates.
Schematic capture – For standard cell digital, analog, RF-like Capture CIS in Orcad by
Cadence and ISIS in Proteus.
Layout – usually schematic-driven layout, like Layout in Orcad by Cadence, ARES in
Proteus

Simulation
Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior,
accurate at device-level.
Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1)
behavior, accurate at boolean-level.
Behavioral simulation – high-level simulation of a design's architectural operation, accurate
at cycle-level or interface-level.
Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed
design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is
called in-circuit emulation.
Technology CAD simulate and analyze the underlying process technology. Electrical
properties of devices are derived directly from device physics

Analysis and verification

Functional verification: ensures
logic design matches
specifications and executes tasks
correctly. Includes dynamic
functional verification via
simulation, emulation, and
prototypes.[7]
RTL Linting for adherence to
coding rules such as syntax,
semantics, and style.[8]
Clock domain crossing verification Schematic capture program
(CDC check): similar to linting, but
these checks/tools specialize in
detecting and reporting potential issues like data loss, meta-stability due to use of multiple
clock domains in the design.
Formal verification, also model checking: attempts to prove, by mathematical methods, that
the system has certain desired properties, and that some undesired effects (such as
deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's RTL-description and
synthesized gate-netlist, to ensure functional equivalence at the logical level.
Static timing analysis: analysis of the timing of a circuit in an input-independent manner,
hence finding a worst case over all possible inputs.
Layout extraction: starting with a proposed layout, compute the (approximate) electrical
characteristics of every wire and device. Often used in conjunction with static timing analysis
above to estimate the performance of the completed chip.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for
cases of interest in IC and PCB design. They are known for being slower but more accurate
 than the layout extraction above.
Physical verification, PV: checking if a design is physically manufacturable, and that the
resulting chips will not have any function-preventing physical defects, and will meet original
specifications.

Manufacturing preparation
Mask data preparation or MDP - The generation of actual lithography photomasks, utilised to
physically manufacture the chip.
Chip finishing which includes custom designations and structures to improve
manufacturability of the layout. Examples of the latter are a seal ring and filler
structures.[9]
Producing a reticle layout with test patterns and alignment marks.
Layout-to-mask preparation that enhances layout data with graphics operations, such as
resolution enhancement techniques (RET) – methods for increasing the quality of the
final photomask. This also includes optical proximity correction (OPC) or inverse
lithography technology (ILT) – the up-front compensation for diffraction and interference
effects occurring later when chip is manufactured using this mask.
Mask generation – The generation of flat mask image from hierarchical design.
Automatic test pattern generation or ATPG – The generation of pattern data
systematically to exercise as many logic-gates and other components as possible.
Built-in self-test or BIST – The installation of self-contained test-controllers to
automatically test a logic or memory structure in the design

Functional safety
Functional safety analysis, systematic computation of failure in time (FIT) rates and
diagnostic coverage metrics for designs in order to meet the compliance requirements for the
desired safety integrity levels.
Functional safety synthesis, add reliability enhancements to structured elements (modules,
RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These
includes (not limited to), addition of error detection and / or correction codes (Hamming),
redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol
checks (Interface parity, address alignment, beat count)
Functional safety verification, running of a fault campaign, including insertion of faults into
the design and verification that the safety mechanism reacts in an appropriate manner for the
faults that are deemed covered.

Companies

Current companies

Market capitalization and company name as of March 2023:

$57.87 billion[10] – Synopsys

$56.68 billion[11] – Cadence Design Systems
AU$4.88 billion[12] – Altium
 ¥77.25 billion[13] – Zuken

Old companies

Market capitalization and company name

as of December 2011:[14]

$2.33 billion – Mentor Graphics;

Siemens acquired Mentor in 2017
and renamed as Siemens EDA in
2021[15][16]
$507 million – Magma Design
Automation; Synopsys acquired
Magma in February 2012[17][18]
NT$6.44 billion – SpringSoft; PCB layout and schematic for connector design
Synopsys acquired SpringSoft in
August 2012

Note: EEsof should likely be on this list,[19] but it does not have a market cap as it is the EDA division of
Keysight.

Acquisitions

Many EDA companies acquire small companies with software or other technology that can be adapted to
their core business.[20] Most of the market leaders are amalgamations of many smaller companies and this
trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a
larger vendor's suite of programs on digital circuitry; many new tools incorporate analog design and mixed
systems.[21] This is happening due to a trend to place entire electronic systems on a single chip.

Technical Conferences on EDA

Design Automation Conference
International Conference on Computer-Aided Design
Design Automation and Test in Europe
Asia and South Pacific Design Automation Conference
Symposia on VLSI Technology and Circuits

See also
Electronics portal

Computer-aided design (CAD)

Circuit design
EDA database
Foundations and Trends in Electronic Design Automation
Signoff (electronic design automation)
Comparison of EDA software
 Platform-based design
Silicon compiler

References
1. "About the EDA Industry" (https://web.archive.org/web/20150802073506/http://www.edac.or
g/industry). Electronic Design Automation Consortium. Archived from the original (http://ww
w.edac.org/industry) on August 2, 2015. Retrieved July 29, 2015.
2. "1966: Computer Aided Design Tools Developed for ICs" (https://www.computerhistory.org/si
liconengine/computer-aided-design-tools-developed-for-ics/). Computer History Museum.
Retrieved January 1, 2023.
3. "EDA (Electronic Design Automation) - Where Electronics Begins" (https://embedjournal.co
m/eda-where-electronics-begins/). Embed Journal. Retrieved January 1, 2023.
4. "Carver Mead Awarded Kyoto Prize by Inamori Foundation" (https://www.caltech.edu/about/
news/carver-mead-awarded-kyoto-prize-by-inamori-foundation). Caltech. Retrieved
January 1, 2023.
5. J. Lienig, J. Scheible (2020). "Chap. 6: Special Layout Techniques for Analog IC Design".
Fundamentals of Layout Design for Electronic Circuits (https://link.springer.com/book/10.100
7/978-3-030-39284-0). Springer. p. 213-256. doi:10.1007/978-3-030-39284-0 (https://doi.org/
10.1007%2F978-3-030-39284-0). ISBN 978-3-030-39284-0. S2CID 215840278 (https://api.s
emanticscholar.org/CorpusID:215840278).
6. Lavagno, Martin, and Scheffer (2006). Electronic Design Automation For Integrated Circuits
Handbook. Taylor and Francis. ISBN 0849330963.
7. "Functional Verification" (https://semiengineering.com/knowledge_centers/eda-design/verific
ation/functional-verification/). Semiconductor Engineering. March 17, 2017. Retrieved
April 10, 2023.
8. BTV RTL Linting. (https://besttechviews.com/rtl-linting-tools-reviews-metrics/) Retrieved
January 2, 2023
9. J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing".
Fundamentals of Layout Design for Electronic Circuits (https://link.springer.com/book/10.100
7/978-3-030-39284-0). Springer. p. 102-110. doi:10.1007/978-3-030-39284-0 (https://doi.org/
10.1007%2F978-3-030-39284-0). ISBN 978-3-030-39284-0. S2CID 215840278 (https://api.s
emanticscholar.org/CorpusID:215840278).
10. "Synopsys, Inc. (SNPS) Stock Price & News - Google Finance" (https://www.google.com/fin
ance/quote/SNPS:NASDAQ). www.google.com. Retrieved March 23, 2023.
11. "Cadence Design Systems Inc (CDNS) Stock Price & News - Google Finance" (https://www.
google.com/finance/quote/CDNS:NASDAQ). www.google.com. Retrieved March 23, 2023.
12. "Altium Limited (ALU) Stock Price & News - Google Finance" (https://www.google.com/finan
ce/quote/ALU:ASX). www.google.com. Retrieved March 23, 2023.
13. "Zuken Inc (6947) Stock Price & News - Google Finance" (https://www.google.com/finance/q
uote/6947:TYO). www.google.com. Retrieved March 23, 2023.
14. Company Comparison - Google Finance (https://www.google.com/finance?q=TPE:2473,TY
O:6947,NASDAQ:LAVA,NASDAQ:MENT,NASDAQ:SNPS,NASDAQ:CDNS). Google.com.
Retrieved on 2013-08-10.
15. "Siemens acquires Mentor Graphics for $4.5 billion, eyes connected device, building
expansion" (https://www.zdnet.com/article/siemens-acquires-mentor-graphics-for-4-5-billion-
eyes-connected-device-building-expansion/). ZDNET. Retrieved March 23, 2023.
16. Dahad, Nitin (December 15, 2020). "Mentor Finally Becomes Siemens EDA From January
2021" (https://www.eetimes.com/mentor-finally-becomes-siemens-eda-from-january-2021/).
EE Times. Retrieved March 23, 2023.
17. Dylan McGrath (November 30, 2011). "Synopsys to buy Magma for $507 million" (https://we
b.archive.org/web/20121025052818/http://www.eetimes.com/electronics-news/4231034/Syn
opsys-to-buy-Magma-for--507-million). EETimes. Archived from the original (http://www.eeti
mes.com/electronics-news/4231034/Synopsys-to-buy-Magma-for--507-million) on October
25, 2012. Retrieved July 17, 2012.
18. "Synopsys to Acquire Magma Design Automation" (http://news.synopsys.com/index.php?s=
20295&item=123337).
19. "Agilent EEsof EDA – Part I" (http://www10.edacafe.com/nbc/articles/view_weekly.php?articl
eid=782353).
20. Kirti Sikri Desai (2006). "EDA Innovation through Merger and Acquisitions" (http://www10.ed
acafe.com/nbc/articles/view_article.php?articleid=301031&interstitial_displayed=Yes). EDA
Cafe. Retrieved March 23, 2010.
21. "Semi Wiki:EDA Mergers and Acquisitions Wiki" (https://web.archive.org/web/20190403080
353/https://www.semiwiki.com/forum/content/). SemiWiki.com. January 16, 2011. Archived
from the original (https://www.semiwiki.com/forum/content/) on April 3, 2019. Retrieved
April 3, 2019.

Notes

http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by

Steven M. Rubin
Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer,
doi:10.1007/978-3-030-39284-0 (https://doi.org/10.1007%2F978-3-030-39284-0)ISBN 978-
3-030-39284-0, 2020
VLSI Physical Design: From Graph Partitioning to Timing Closure, by Kahng, Lienig, Markov
and Hu, doi:10.1007/978-90-481-9591-6 (https://doi.org/10.1007%2F978-90-481-9591-6)
ISBN 978-90-481-9590-9, 2011
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and
Scheffer, ISBN 0-8493-3096-3, 2006
The Electronic Design Automation Handbook, by Dirk Jansen et al., Kluwer Academic
Publishers, ISBN 1-4020-7502-2, 2003, available also in German ISBN 3-446-21288-4
(2005)
Combinatorial Algorithms for Integrated Circuit Layout, by Thomas Lengauer, ISBN 3-519-
02110-2, Teubner Verlag, 1997.

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