11.

HALF ADDER

 HALF ADDER is a combinational circuit designed to add two single bit numbers. It contains two
inputs and two outputs.

BLOCK DIAGRAM

TRUTH TABLE

INPUT
A B
0 0
0 1
1 0
1 1
OUTPUT
SUM CARRY
0 0
1 0
1 0
0 1

K-MAP FOR SUM

A/B 0 1
0 0 1
1 1 0

K-MAP FOR CARRY

A/B 0 1
0 0 0
1 0 1
 CIRCUIT DIAGRAM OF HALF ADDER
12.FULL ADDER
 IT is an arithmetic logic circuit that is designed to add two single bit numbers with carry.

BLOCK DIAGRAM

TRUTH TABLE

INPUT 0UTPUT
A B CIN SUM CARRY OUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

K-MAP FOR SUM

A/BC 00 01 11 10
0 0 1 0 1
1 1 0 1 0
 K-MAP FOR CARRY

A/BC 00 01 11 10
0 0 0 1 0
1 0 1 1 1

13.HALF SUBTRACTOR
 It is a combinational circuit used to get the difference between two single bit numbers.

BLOCK DIAGRAM

TRUTH TABLE

INPUT OUTPUT
 A B
0 0
0 1
1 0
1 1
D B
0 0
1 1
1 0
0 0

K-MAP FOR DIFFERENCE

A/B 0 1
0 0 1
1 1 0

K-MAP FOR BORROW(BOUT)

A/B 0 1
0 0 1
1 0 0

14.FULL SUBTRACTOR
 FULL SUBTARCTOR is a combinational circuit used to perform subtraction among three bits.

BLOCK DIAGRAM

TRUTH TABLE
INPUT 0UTPUT
A B BIN D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0

K-MAP FOR DIFFERENCE

A/BC 00 01 11 10
0 0 1 0 1
1 1 0 1 0

K-MAP FOR BORROW(BOUT)

A/BC 00 01 11 10
0 0 1 1 1
1 0 0 1
15.XOR GATE:
> It produce low input if all input are low or if all input are high.
Gate symbol

LOGIC DIAGRAM OF XOR GATE

Truth table:
INPUTS output
A B A’B+AB’
0 0 0
0 1 1
1 0 1
1 1 0

TIMING DIAGRAM:

VENN DIAGRAM:
Expression:
A and B are inputs ,+is operator and f output. F=A’B+AB

16 XNOR GATE:
 It produce high ouput if all input are high or low.
Gate symbol:

Logic expression;
A and B are inputs operator and f output.
TIMING DIAGRAM:

VENN-DIAGRAM
Truth table:

INPUTS output
A B A’B’
0 0 1
0 1 0
1 0 O
1 1 1

17.RS FLIP-FLOP

> The flip-flops changes its states

only when clock pulse is applied
depending upon inputs. The
circuit is formed by adding two
and gates at inputs of RS flip=flop.

Fig: block diagram of RS flip-flop.

TRUTH TABLE

CLK S R Q(n+1)
0 x X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 invalid

CHARACTERISTICS TABLE

Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Invalid
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 invalid

K map
 Qn 00 01 11 10
0 0 0 x 1
1 1 0 X 1
Expression= S+QnR’

Excitation table

Qn Qn+1 S
0 0 0
0 1 1
1 0 0
1 1 x
Conclusion

At standard running of SR NAND

FLIP-FLOP BOTH NAND INPUTS
MUST NORMALLY BE 1 LEVEL.

18.D FLIP-FLOP
D flip-flop is also known as delay flip flop attach with SR flip flop by attaching not gate in reset.

FIG: BLOCK DIAGRAM OF D FLIP FLOP.

LOGIC DIAGRAM:

FIG: LOGIC DIAGRAM OF D FLIP-FLOP.

TRUTH TABLE

CLK D Qn+1
0 X Qn
1 0 0
1 1 1
CHARACTERISTICS TABLE

Qn D Qn+1

0 0 0

0 1 1

1 0 0

1 1 1

Expression

Qn+1=D

EXCITATION TABLE

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

Conclusion

It ensures that at that same time, both the inputs and R are never equal to 1.
 19.JK FLIP-FLOP
> JK Flip Flop is a
universal flip flop
having two inputs ‘J’
and ‘K’.

Fig: block diagram of jk flip flop.

LOGICAL DIAGRAM OF JK FLIP FLOP

TRUTH TABLE

CLK J K Q(n+1)
0 x X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 (Qn)’

Q = 1 & Q’ = 0

CLK = 1, J
= 1, K=1
Q= 0&
Q’ = 1=
(Qn)’

CHARACTERISTICS TABLE
 Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

K map Qn+1

Qn/jk 00 01 11 10
0 0 0 1 1
1 1 0 0 1

Excitation table

Qn Qn+1
0 0
0 1
1 0
1 1
j k
0 x
1 x
x 1
x 0

Conclusion

The sequential operation of the JK flip-flop is exactly the same as for the previous SR flip-flop with the
same set and reset inputs. Difference is it has no invalid or forbidden input states
20. T FLIP-FLOP
Toggle flop flop which changes its output on each clock edge given an output which is half the
frequency of the signal to T input.
 LOGIC DIAGRAM

TRUTH TABLE

CLK T Qn+1
0 X Qn
1 0 Qn
1 1 Qn’

CHARACTERISTICS TABLE

Qn
0
0
1
1

EXCITATION TABLE

Qn Qn+1 T
 0 0 0
0 1 1

1 0 1
1 1 0

CONCLUSION

Whenever the clock is low, the input is never going to affect the output state. The clock has to be high
for the inputs to get active.