TITLE6 LOREM

Chapter – Functions
IPSUM Logic
of Combinational
Dr. Muhammad Hanif
Contents
◦ 6–1 Adders
◦ Half and Full Adder
◦ Parallel Binary Adders
◦ Ripple Carry and Look-Ahead Carry Adders

◦ 6–4 Comparators
◦ 6–5 Decoders
◦ 6–6 Encoders
◦ 6–7 Code Converters
◦ 6–8 Multiplexers (Data Selectors)
◦ 6–9 Demultiplexers
◦ 6–10 Parity Generators/Checkers
 Adders
◦ Adders are important in computers and also in other types of digital systems in which
numerical data are processed.
◦ A basic Binary Adder circuit can be made from standard AND and Ex-OR gates.
◦ The addition of two digits produces an output called the SUM of the addition and a
second output called the CARRY or Carry-out, ( COUT ) bit
◦ An understanding of the basic adder operation is fundamental to the study of
digital systems
◦ Goal of this section is to understand different types of adders
1. Half-Adder
2. Full-Adder
3. Parallel Multi-bit Adder
4. Ripple Carry Adder
5. Look Ahead Adder
 Adder: Half Adder
Basic rules of binary addition are performed by a half adder,
which has two binary inputs (A and B) and two binary
outputs:
Carry out and Sum .
Inputs Outputs
The inputs and outputs can be summarized on a truth table. A B Cout S
The logic symbol and equivalent circuit are: 0 0 0 0
S S 0 1 0 1
A S
1 0 0 1
1 1 1 0
A
B Cout Cout
B
Adder: Half Adder
◦ Addition rules of two binary numbers:

0 0 1 1
+0 +1 +0 +1
(carry) 1←
0 1 1
0
Adder: Half Adder
◦ The SUM part in the half adder is similar to the output of a two inputs Ex-OR gate.

Symbol Truth Table

B A S

0 0 0

0 1 1
2-input Ex-OR Gate
1 0 1

1 1 0
Adder: Half Adder
◦ The carry bit is similar to the two inputs AND gate operation:

Symbol Truth Table

B A C

0 0 0

0 1 0
2-input AND Gate
1 0 0

1 1 1
Adder: Half Adder
◦ The half adder can be implemented uing Ex-OR and AND Gate:

Symbol Truth Table

CARR
B A SUM
Y

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Adder: Half Adder
◦ The Boolean Expression for the half adder Sum and Carry are:
◦ For the SUM bit:
◦ SUM = A XOR B = A ⊕ B
◦ For the CARRY bit:
◦ CARRY = A AND B = A.B
Adder: Half Adder
◦ One major disadvantage of the Half Adder circuit is that there is no provision
for a “Carry-in” from the previous circuit when adding together multiple data
bits.
◦ The most complicated operation the half adder can do is “1 + 1” .
◦ One simple way to overcome this problem is to use a Full Adder type binary
adder circuit.
Adder: Full Adder
◦ The main difference between the Full Adder and the Half Adder is that a full
adder has three inputs.
◦ Two single bit data inputs A and B plus an additional Carry-in (C-in) input to
receive the carry from a previous stage.

A full-adder can be constructed from two half adders as shown: Inputs Outputs
A B Cin Cout S
S S 0 0 0 0 0
A A S A S Sum
0 0 1 0 1
A S 0 1 0 0 1
B 0 1 1 1 0
B Cout B Cout B
Cin 1 0 0 0 1
Cout Cin Cout
1 0 1 1 0
1 1 0 1 0
Cout 1 1 1 1 1
Adder: Full Adder
Symbol Truth Table

◦ Truth Table
C-in B A Sum C-out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
Adder: Full Adder
◦ The Boolean expression for a full adder is as follows.
◦ For the SUM (S) bit:
◦ SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
◦ For the CARRY-OUT (Cout) bit:
◦ CARRY-OUT = A AND B OR Cin (A XOR B) = A.B + Cin.(A ⊕ B)
 Adder: Full Adder
S S
1 A S 1 A S 0
For the given inputs, determine
the intermediate and final outputs 0 B Cout 0 B Cout
of the full adder. 1
1
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0. 1

The second half-adder has inputs of 1 and 1; therefore the

Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.
Adder: Parallel Adder
◦ A single full-adder is capable of adding two 1-bit numbers and an input
carry.
◦ To add binary numbers with more than one bit, you must use additional full-
adders.
◦ When one binary number is added to another, each column generates a
sum bit and a carry bit to the next column to the left.
◦ Thus, two or more Full adders can be combined into parallel adders that can
add binary numbers with multiple bits.
Adder: Parallel Adder
◦ Example
Adder: Parallel Adder
A 4-bit Parallel Adder is shown.

A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S4 S3 S2 S1
 Adder: Parallel Adder
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a
carry in (labeled (C0) and a Carry out (labeled C4).

S
1 1
2 2
Binary 4-bit sum
3 3
number A 4 4

1
Binary 2
3
number B
4

Input Output
carry C0 C4 carry
Adder: Parallel Adder
Cascading to add more number of bits by using 4-bit adders
• LHS adder  for addition of most significant 4 bits addition
• RHS adder  for addition of least significant 4 bits addition
Adder: Example

◦ Vote Counting System

Parallel Binary Adder
◦ Parallel adders can be placed into two categories based on the way in
which internal carries from stage to stage are handled.
◦ Those categories are
1. Ripple carry
2. Look-ahead carry.
◦ Externally, both types of adders are the same in terms of inputs and
outputs.
◦ The difference is the speed at which they can add numbers.
◦ The look-ahead carry adder is much faster than the ripple carry adder.
 Ripple Carry Adder
• Carry output of each full-adder is connected to the carry input of the next higher-order stage
• The sum and the output carry of any stage cannot be produced until the input carry occurs
for each full adder  causes a time delay in the addition process

• Input carry to the least significant stage has to ripple through all the adders
before a final sum is produced
 Look Ahead Adder
◦ In ripple adder, speed of addition limited by the time required for the
carries to ripple through all the adder stages
◦ One method of speeding up  Look-ahead Adder
◦ anticipates the output carry of each stage
◦ produces the output carry by either carry generation or carry propagation

◦ Carry generation occurs when an output carry is produced

(generated) internally by the full-adder.
◦ A carry is generated only when both input bits are 1s.
◦ Carry propagation  occurs when the input carry is rippled to
become the output carry  when either or both of the input bits
are 1s.
Look Ahead Carry Adder
◦ The output carry of a full-adder can be expressed in terms of both the
generated carry (Cg) and the propagated carry (Cp).
◦ The output carry (Cout) is a 1 if the generated carry is a 1 OR if the propagated
carry is a 1 AND the input carry (Cin) is a 1.
 Look Ahead Carry Adder
• Let us now apply the concept of a look-ahead carry
to a parallel multi-bit adder

• All the output carries can be generated without any delay!

 Look Ahead Carry Adder
◦ The Cout equations are implemented with logic gates and connected to the full-adders to create a 4-bit look-
ahead carry adder