An Investigatory Project

On

“LOGIC GATES “

For the partial fulfillment of

AISSCE Physics Practical Examination-2019

Prepared By:
Name :
Class /Sec :
Roll No :
Board Roll No. :

Guided By:
Mr. Subrat Ranjan Pathi, PGT Physics
Mr. Purna Chandra Bhuyan, PGT Physics
 CERTIFICATE

This is to certify that Master …………………………………………………………

of std. XII ‘……’, Roll No. ------ of D.A.V Public School, Berhampur (GM), has

successfully completed the investigatory project on

‘Light Dependent Resistor (LDR)‘ under guidance of Mr. Subrat Ranjan

Pathi , PGT Physics and Mr. Purna Chandra Bhuyan , PGT Physics for the

partial fulfillment of AISSCE Physics Practical Examination -2019.

Signature of Subject Teacher

Signature of Internal Examiner Signature of External Examiner

ACKNOWLEDGEMENT
 INDEX

SL. CONTENT Page

No. no.
1 Objective 1
2 Apparatus Required 2
3 Theory 3
4 Circuit diagram 4
5 Conclusion
6 Precaution
7 Sources of error
8 Bibliography
 OBJECTIVE
To design basic logic gates and their combination form
NAND and NOR gate with appropriate truth table
 APPARATUS
I) 2 battery of 9V
II) 09 switches
III) 10 LEDs
IV) Connecting wires
V) Hard board
 THEORY
The three logic gates and their combination
are the building block of the digital circuit.
I. OR-gate :
A logic gate in which the output is high, if at least one input is high.
SYMBOL:

Truth table
INPUT OUTPUT
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

II. AND-gate
A logic gate which gives high output is, only if all inputs are high.
SYMBOL

TRUTH TABLE
 INPUT OUTPUT
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

III. NOT-gate
A logic gate which gives high output is, input is low and vice versa.
SYMBOL

TRUTH TABLE

INPUT OUTPUT
A Y=A’
0 1
1 0

IV. NAND-gate
When the out of an AND gate given as input to a NOT gate , the
system so obtained known as NAND gate.
SYMBOL

TRUTH TABLE
 INPUT OUTPUT
A B Y’=A.B Y=(A.B)’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
V. NOR-gate
When the out of an OR gate given as input to a NOT gate , the system
so obtained known as NAND gate.

SYMBOL

TRUTH TABLE
INPUT OUTPUT
A B Y’=A+B Y=(A+B)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
 CIRCUIT DIAGRAM
OR gate

AND gate

NOT gate
NAND gate

NOR gate
CONCLUSION:
PRECAUTION
SOURCES OF ERROR
BIBLIOGRAPHY
Cover Page (Photo Print glossy paper)