Electrical Engineering Department

Module; [13ELEC13C] Digital Design

Sheet 4
Sequential Logic Design

Sheet four
Sequential Logic Design

1) Given the input waveforms shown in figure 1 sketch the output Q, of a D latch.

Figure 1

2) Given the input waveforms shown in figure 1 sketch the output Q, of a D flip-
flop

3) For a gated D latch, the waveforms shown in Figure 2 are observed on its inputs.
Draw the timing diagram showing the output waveform you would expect to see
at Q

Figure 2

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4) Draw the Q output relative to the clock for a D flip-flop with the inputs as shown
in Figure 3. Assume positive edge-triggering and Q initially LOW.

Figure 3

5) Design a shifter that always shifts 32-bit input left by 2 bits. The input and output
are both 32 bits. (a) Explain the design in words and sketch a schematic.
(b) Implement your design using VHDL

6) Show the states of the 5-bit register in Figure 4 for the specified data input and
clock waveforms. Assume that the register is initially cleared (all 0s).

Figure 4

7) For the serial in/serial out shift register, determine the data-output waveform for
the data-input and clock waveforms in Figure 5. Assume that the register is
initially cleared.

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 Figure 5

8) Using four registers, design a circuit that stores the previous four values seen at an
8-bit input D. The circuit should have a single 8-bit output that can be configured
using two inputs s1 and s0 to output any one of the four registers
(Hint: use an 8 bit 4x1 mux.)

9) Implement a 4-bit register with the functionality specified in the following table.
(A = a3a2a1a0 is the output of the register.)
NOTE: Specify the select lines of each multiplexer as well as the inputs. You can
use the following components if needed.
 Comparator
 Logic gates
 Multiplexers

S1S2 Action Output

00 Load b3b2b1b0
01 Keep current value A
10 if(B>A) Load B/2; else Load B*2 if (B>A) B/2; else B*2
11 if(B>A/2) Load B; else keep current value if(B<A/2) B; else A

10) Design a 4-bit register with 2 control inputs s1 and s0, 4 data inputs I3..I0, and 4
data outputs Q3..Q0. The function table below shows the configurations for the
register.

S1S2 Action
00 Clear the contents of the register
01 Load I
10 Shift right by one bit
11 Shift left by one bit

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